Signed In-Memory MAC Array With Dynamic Activation Timing
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Solution Overview
Problem
Existing in-memory computation (IMC) devices require long elaboration times for performing signed multiply-and-accumulate (MAC) operations, limiting the number of operations per second due to the need to handle positive and negative values.
Innovation Solution
The IMC device employs a computation memory array with positive and negative memory cells activated by specific duration signals, using a row-activation circuit to control activation durations based on input value signs and absolute values, optimizing the MAC operation through phased activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If known approaches are used for performing signed MAC operations, then the device can handle positive and negative values, but the elaboration time becomes long
Solution Approach 1:
The patent divides the memory array into separate positive and negative memory cell groups, and segments the activation process into distinct positive and negative activation signals with different durations. This segmentation allows independent optimization of activation times for positive and negative values, enabling faster signed MAC operations without compromising the ability to handle both positive and negative inputs
Solution Approach 2:
The patent implements dynamic activation durations for positive and negative wordlines based on the sign and absolute value of input values. The row-activation circuit dynamically adjusts the duration of positive-activation and negative-activation signals, allowing the system to adaptively optimize elaboration time for different input combinations while maintaining full support for signed arithmetic
2Measurement precision
If the activation duration is extended to ensure complete elaboration, then accuracy is maintained, but the number of operations per second decreases
Solution Approach 1:
The patent changes the activation duration parameter dynamically based on the input value characteristics. By adjusting the duration of positive-activation and negative-activation signals according to the sign and absolute value of inputs, the system maintains computational accuracy for all cases while reducing the average elaboration time, thereby increasing operations per second
3Adaptability or versatility
If separate positive and negative memory cells are used, then signed operations are enabled, but the device complexity increases
Solution Approach 1:
The patent segments the memory array into positive and negative memory cell groups, each associated with dedicated wordlines. This segmentation enables signed MAC operations by allowing independent activation of positive or negative cells based on input signs, while the segmented structure actually simplifies the control logic compared to a unified approach that would need to handle sign bits separately
Data Source
AI summary
An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.