Signed MAC In-Memory Computing With Dual-Polarity Cell Activation

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Solution Overview

Problem

Existing in-memory computation (IMC) devices require long elaboration times for performing signed multiply-and-accumulate (MAC) operations, limiting the number of operations per second due to the need for handling positive and negative values.

Innovation Solution

The IMC device organizes memory cells into positive and negative subsets, activating them with duration-specific signals based on the sign and absolute value of input values, allowing for a linear combination of currents that determine the output, using a row-activation circuit and column-elaboration circuit to process the bitline current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If known approaches are used for performing signed MAC operations, then the device can handle positive and negative values, but the elaboration time becomes long

Engineering Contradiction:

Improveability to handle signed valuesVSAvoidelaboration time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The memory array is segmented into positive and negative sub-arrays, with each handling one sign type. This segmentation allows parallel processing of positive and negative MAC operations simultaneously, reducing the total elaboration time while maintaining the ability to handle signed values.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention uses periodic activation signals with different durations to control the timing of operations in positive and negative sub-arrays. By carefully designing the activation periods and durations, the system performs signed MAC operations in a time-efficient periodic manner.

Inventive Principle:

Principle #19Periodic action

2Adaptability or versatility

If known approaches are used for performing signed MAC operations, then the device can process signed data, but the number of operations per second becomes low

Engineering Contradiction:

Improveability to perform signed MAC operationsVSAvoidnumber of operations per second

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

By dividing the memory array into positive and negative sub-arrays that operate in parallel, the system doubles the throughput of signed MAC operations. Each sub-array can process operations simultaneously without interfering with the other, thereby increasing the number of operations per second.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention merges the functionality of separate positive and negative MAC operation circuits into a unified memory array structure. This merging allows both types of operations to share the same physical infrastructure while maintaining parallel execution capability, improving productivity.

Inventive Principle:

Principle #5Merging (Combining)

3Loss of time

If separate positive and negative subsets of memory cells are used, then the elaboration time is reduced, but the device complexity increases

Engineering Contradiction:

Improveelaboration timeVSAvoidmemory array structure

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The positive and negative sub-arrays use identical memory cell structures and activation mechanisms, making the design universal and scalable. This multi-functionality allows the same basic cell design to serve dual purposes (handling both positive and negative values), reducing the actual complexity increase despite the functional division.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces the elaboration time for signed MAC operations, enhancing the computational efficiency and throughput of the IMC device.

Implementation Method 1

each group of memory cells including a positive subset of cells coupleable to a respective positive wordline and a negative subset of cells coupleable to a respective negative wordline

Methodology Applied

Scientific EffectOhm's Law: Ohm's Law

Implementation Method 2

a row-activation circuit configured to receive the input signal and to provide, for each input value, during an elaboration interval having an elaboration duration, a positive-activation signal having a positive-activation duration

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12586637B2In-memory computation device for performing a signed MAC operation

Publication Date: 2026.03.24 STMICROELECTRONICS INT NV

AI summary

An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.