Signed Value Multiplier Circuit Using Shared Memory Splices

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Solution Overview

Problem

Existing digital circuits for multiplying signed numbers are complex and lack simplicity, particularly when dealing with signed values and constants.

Innovation Solution

A multiplier circuit that separates a signed value into multiple splices, utilizing shared and separate memories to generate partial products, which are then summed by an addition circuit to efficiently multiply the signed value by a constant.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If digital circuits use traditional multiplication methods for signed numbers, then multiplication function is achieved, but circuit complexity increases

Engineering Contradiction:

Improvecircuit complexityVSAvoidmultiplication function

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The signed value is divided into multiple splices (e.g., sign portion and magnitude portion), allowing the multiplication circuit to handle signed numbers by processing each splice separately and combining results, thereby reducing overall circuit complexity while maintaining multiplication functionality

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A shared memory structure is used to store partial products for multiple splices, allowing the same memory resource to serve multiple multiplication operations simultaneously, reducing the number of dedicated storage locations needed and simplifying the circuit

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Quantity of substance

If separate memories are used for each splice, then partial products are stored, but storage locations increase

Engineering Contradiction:

Improvestorage locationsVSAvoidcircuit implementation

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

Multiple separate memory structures for different splices are merged into a single shared memory. The shared memory uses a subset relationship where the storage locations readable for less significant splices are a subset of those readable for more significant splices, reducing total storage requirements while maintaining ease of manufacture

Inventive Principle:

Principle #5Merging (Combining)

3Device complexity

If more adders are used to sum partial products, then multiplication accuracy is improved, but circuit complexity increases

Engineering Contradiction:

Improvecircuit complexityVSAvoidmultiplication accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The addition operation is segmented into multiple stages corresponding to different splices. Each stage sums partial products for specific splices, and the results are progressively combined. This segmented approach maintains multiplication accuracy while reducing the number of adders needed compared to a single large adder

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8843541B1Circuit and method for multiplying a signed value by a constant

Publication Date: 2014.09.23 XILINX INC

AI summary

A multiplier circuit and method multiply a signed value by a constant. The signed value received at an input port is separable into two or more splices. A first splice is a most significant one of the splices, and a second splice is another one of the splices. One or more memories provide respective partial products for the splices, and these memories include a shared memory. The shared memory provides the respective partial products for the first and second splices from storage locations in the shared memory. The storage locations that are readable to provide the respective partial product for the second splice are a subset of the storage locations that are readable to provide the respective partial product for the first splice. An addition circuit sums the respective partial products for the splices.