Signed Multiplier Circuit Using Uniform Logic Block Array
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Solution Overview
Problem
Existing multiplier circuits in integrated circuits are not optimally designed for programmable ICs, particularly in terms of regularity and efficiency, which complicates clock network design and consumes significant engineering resources, and they lack flexibility for compute-intensive applications like digital signal processing.
Innovation Solution
A signed multiplier circuit utilizing a two-dimensional array of substantially similar logic blocks, each capable of performing four different multiply functions, allowing for the combination of rows and columns to build large multipliers of various sizes, with programmable AND gates and memory cells for inverted outputs and multiplexer control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional multiplier circuits with multiple cell types are used, then multiplication functionality is achieved, but device regularity and ease of manufacture deteriorate
Solution Approach 1:
The patent applies universality by designing a single standardized logic block that can perform multiple multiplication operations (signed-signed, unsigned-unsigned, signed-unsigned, and unsigned-signed) through configuration. This eliminates the need for different cell types for different multiplication modes, thereby improving device regularity and ease of manufacture while maintaining full multiplication functionality.
Solution Approach 2:
The patent uses parameter changes by configuring the standardized logic block with different control signals and data inputs to switch between various multiplication modes. By changing the parameters (input signal interpretations and control logic states) rather than the physical structure, the same hardware can perform different functions, reducing device complexity.
2Speed
If Wallace tree architecture is used, then multiplication speed is improved, but device regularity and suitability for array-type ICs deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the multiplication process into multiple stages using identical logic blocks arranged in an array. Each block handles a specific portion of the computation (partial product generation and addition), and the segmented stages are connected in a regular pattern. This maintains device regularity while achieving improved speed through parallel processing across the segmented blocks.
Solution Approach 2:
The patent transitions from the planar Wallace tree structure to a multi-dimensional array configuration of standardized logic blocks. By organizing the computation in a two-dimensional array with regular interconnections, the patent achieves both speed improvement through parallelism and maintained regularity suitable for array-type integrated circuits.
3Adaptability or versatility
If programmable elements are added to each logic block, then flexibility and adaptability are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies universality by incorporating programmable elements into the standardized logic block that can be configured to perform any of the four multiplication modes. The same programmable structure serves multiple functions, providing flexibility without requiring different hardware for different operations, thus limiting the increase in device complexity.
Solution Approach 2:
The patent merges the programmable configuration elements with the multiplication logic in an integrated manner within each standardized block. By combining the configuration memory and logic functions into a unified structure with regular interconnections, the patent reduces manufacturing difficulty compared to separate programmable and logic components.
Data Source
AI summary
A signed multiplier circuit includes a two-dimensional array of substantially similar logic blocks. Each of the logic blocks is programmable to implement any of four multiply functions of first and second inputs, in which: the first and second inputs are both signed; the first and second inputs are both unsigned; the first input is signed and the second input is unsigned; and the first input is unsigned and the second input is signed. Each logic block includes rows and columns of sub-circuits, e.g., logical AND gates and full adders. One row and one column of each logic block include a programmably invertible AND gate, with the row and column being independently controlled. The ability to program the logic block to perform all four of these functions enables the combination of rows and columns of the logic blocks to build large signed multipliers of virtually any size.