Synchronized SIL Simulation With Time-Master FPGA Coordination
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional software-in-the-loop (SIL) simulations using FPGA models are not time-synchronous and are event-based or operate in a virtual time domain, making them unsuitable for high-performance simulations, particularly in electric machines, and cannot be effectively coupled with real FPGA hardware for acceleration.
Innovation Solution
A method for synchronized SIL simulation is implemented by loading a first simulation component onto a computing farm with a computing module and a second component onto an accelerator farm with an accelerator module, where the components have different simulation step sizes, and a time master triggers the execution of simulation steps to ensure synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FPGA models are used in conventional SIL simulations, then simulation speed is improved, but time-synchronization is lost and the simulation operates in a virtual time domain
Solution Approach 1:
A time master component is introduced as an intermediary to coordinate between the processor-based first simulation component and the FPGA-based second simulation component. The time master receives trigger signals, determines the number of FPGA time steps required, and generates corresponding trigger signals for the FPGA, ensuring synchronized operation between heterogeneous components with different time domains
Solution Approach 2:
The system dynamically adjusts the simulation step size of the FPGA component based on the ratio between the first simulation step size (processor) and the second simulation step size (FPGA). By calculating the required number of FPGA time steps and adjusting trigger signal frequency, the system maintains time-synchronization while allowing the FPGA to operate at its native high speed
2Adaptability or versatility
If processor-based emulation is used for FPGA configuration, then implementation flexibility is improved, but simulation performance deteriorates by several orders of magnitude
Solution Approach 1:
The simulation model is segmented into two distinct components: a processor-based first simulation component for non-time-critical functions and an FPGA-based second simulation component for time-critical functions. This segmentation allows each component to operate in its optimal performance domain while maintaining overall system flexibility through standardized interfaces
Solution Approach 2:
The system replaces pure processor-based emulation with a hybrid architecture that substitutes FPGA hardware acceleration for the time-critical second simulation component. This substitution maintains implementation flexibility through programmable logic while achieving performance improvement by several orders of magnitude for time-sensitive simulations
3Productivity
If different simulation step sizes are used for processor and FPGA components, then execution efficiency is improved, but synchronization complexity increases
Solution Approach 1:
The time master acts as a mediator that absorbs the synchronization complexity, translating between the different time domains of the processor and FPGA components. It calculates the step size ratio, determines trigger signal frequency, and coordinates execution without requiring the individual components to directly manage synchronization complexity
Solution Approach 2:
The system implements a feedback mechanism where the time master monitors the execution state of both simulation components and dynamically adjusts trigger signal generation. The FPGA component's completion status feeds back to the time master, which then determines when to issue the next trigger signal, ensuring synchronized operation despite different step sizes
Data Source
AI summary
A method for synchronized software-in-the-loop (SIL) simulation includes: loading a first simulation component onto a computing farm with at least one computing module and a second simulation component onto an accelerator farm with at least one accelerator module, wherein the first simulation component is provided for a computer module, wherein the second simulation component is provided for an accelerator module; specifying a time master that triggers an execution of the first simulation component and the second simulation component, wherein a trigger initiates the execution of a simulation step comprising a time step of the first simulation component and a plurality of time steps of the second simulation component; and performing the synchronized SIL simulation by repeatedly triggering simulation steps, wherein a respective new simulation step is triggered upon the first and second simulation components having finished calculations of a respective current simulation step.