Silica Layer Shrinkage Control via SiO2 Conversion Rate

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Solution Overview

Problem

The formation of silica layers from silicon-containing polymers during semiconductor manufacturing often results in layer stress and cracking due to high shrinkage rates, which deteriorate the reliability of devices.

Innovation Solution

A composition for forming a silica layer with a controlled SiO2 conversion rate between 0 and 15, incorporating a silicon-containing polymer such as polysilazane or polysiloxazane, and a solvent, which limits layer shrinkage and enhances wet etch rate characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a composition including a silicon-containing polymer is coated on a substrate and converted into a silica layer, then the silica layer can be formed for use as an insulation layer, but layer stress is generated which causes cracking during semiconductor manufacturing, reducing device reliability

Engineering Contradiction:
Improvedevice reliabilityVSAvoidlayer strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent applies parameter changes by precisely controlling the SiO2 conversion rate within a specific range (greater than 0 and less than or equal to 15) through controlled hydrolysis and condensation reactions. This parameter control optimizes the balance between layer formation and stress reduction, preventing cracking while maintaining insulation functionality. The conversion rate is controlled by adjusting reaction conditions such as moisture exposure time and temperature during the curing process.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If the SiO2 conversion rate is increased to improve silica layer formation, then the layer shrinkage rate increases causing more cracking, but if the conversion rate is decreased too much, the silica layer formation becomes insufficient

Engineering Contradiction:
Improvesilica layer formation qualityVSAvoidlayer shrinkage rate
Core Design Contradiction:
Manufacturing precisionVSStability of the object's composition

Solution Approach 1:

The patent optimizes the SiO2 conversion rate parameter within a specific range (greater than 0 and less than or equal to 15) to achieve the desired balance. This parameter optimization ensures sufficient silica layer formation while limiting shrinkage-induced stress that causes cracking.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies partial action by controlling the hydrolysis and condensation reactions to achieve a moderate SiO2 conversion rate rather than complete conversion. This partial conversion (greater than 0 and less than or equal to 15) is sufficient to form an functional insulation layer while avoiding the excessive shrinkage and stress that would occur with complete conversion, thereby preventing cracking.

Inventive Principle:
Principle #16Partial or excessive action

3Ease of manufacture

If a conventional silica layer is formed, then it provides insulation, but it has poor wet etch rate characteristics in pattern gaps

Engineering Contradiction:
Improvewet etch rate characteristicsVSAvoidpattern gap quality
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the chemical composition parameters of the silica layer by controlling the SiO2 conversion rate and the nature of the silicon-containing polymer. This compositional adjustment improves wet etch rate characteristics in pattern gaps, enabling better manufacturing control and pattern definition while maintaining the insulation function.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The controlled SiO2 conversion rate reduces layer shrinkage to 13-15.5% and improves wet etch rate characteristics, preventing cracking and enhancing the reliability and performance of electronic devices.

Implementation Method 1

a composition for forming a silica layer which may include a silicon-containing polymer and a solvent, wherein the composition has a SiO2 conversion rate of greater than about 0 and less than or equal to about 15

Methodology Applied
Scientific EffectHydrolysis: Hydrolysis

Implementation Method 2

SiO2 conversion rate=(a ratio of an area of Si—O to an area of Si—H measured after coating the composition in a thickness of 6700 Å on a bare wafer, and allowing the coated wafer to stand for 24 hours under conditions of a temperature of 85° C. and a relative humidity of 85%)

Methodology Applied
Scientific EffectCondensation: Condensation

Implementation Method 3

allowing the coated wafer to stand for 24 hours under conditions of a temperature of 85° C. and a relative humidity of 85%

Methodology Applied
Scientific EffectHeat treatment: Heating

Implementation Method 4

a relative humidity of 85%

Methodology Applied
Scientific EffectHumidity absorption: Absorption (physical)

Implementation Method 5

The shrinkage rate of the silica layer may range from about 13% to about 15.5%. The shrinkage rate may be represented by: Layer shrinkage rate (%)=(layer thickness before wet curing−layer thickness after wet curing)/(layer thickness before wet curing)×100%

Methodology Applied
Scientific EffectThermal contraction: Thermal Contraction

Data Source

PatentUS10804095B2Composition for forming silica layer, silica layer, and electronic device
Publication Date: 2020.10.13 SAMSUNG SDI CO LTD
  • US10804095B2 patent drawing
  • US10804095B2 patent drawing
  • US10804095B2 patent drawing

AI summary

A composition for forming a silica layer includes a silicon-containing polymer and a solvent, the composition having a SiO2 conversion rate of greater than about 0 and less than or equal to about 15. The SiO2 conversion rate is represented by: SiO2 conversion rate=(a ratio of an area of Si—O to an area of Si—H measured after coating the composition in a thickness of 6700 Å on a bare wafer, and allowing the coated wafer to stand for 24 hours under conditions of a temperature of 85° C. and a relative humidity of 85%)−(a ratio of an area of Si—O to an area of Si—H measured after coating the composition in a thickness of 6700 Å on a bare wafer, and allowing the coated wafer to stand for 2 hours under conditions of a temperature of 85° C. and a relative humidity of 85%).