Silicate Gate Stack for Multi-Vt CMOS Scaling

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Solution Overview

Problem

Conventional methods for creating multi-threshold voltage semiconductor devices face challenges in scaling to smaller sizes due to the merging of thick work function metal stacks and increased variations in electron work function, which affect the threshold voltage control at extreme scaled nodes.

Innovation Solution

A method involving a silicate layer on a CMOS device channel, a high dielectric constant layer, and a work function metal layer, followed by a low temperature anneal, allows for precise control of threshold voltage shifts by varying the silicate layer thickness by up to one nanometer, enabling multi-Vt transistors at more extreme scaled nodes without increasing the overall stack thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a thick work function metal stack is used to provide desired threshold voltage shift, then the Vt control is improved, but the stack merges at lower spacings

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidstack thickness
Core Design Contradiction:
Manufacturing precisionVSLength of moving object

Solution Approach 1:

The patent changes the material parameter from conventional work function metals to silicate materials (such as barium silicate, strontium silicate, lanthanum silicate) that provide equivalent or superior threshold voltage control with reduced thickness. This material substitution enables achieving the same Vt shift with a thinner layer, preventing stack merging at scaled nodes.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures combining silicate layers with high dielectric constant materials to achieve both threshold voltage control and electrical performance. The silicate-high dielectric constant material composite provides the necessary electrical characteristics while maintaining reduced thickness compared to conventional metal stacks.

Inventive Principle:
Principle #40Composite materials

2Manufacturing precision

If conventional work function metal stacks are used at scaled nodes, then Vt control is achieved, but variations in electron work function increase

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidelectron work function variation
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent transitions from metal-based work function control to silicate-based control, fundamentally changing the material parameter. Silicate materials exhibit more stable electron work function characteristics at scaled nodes, reducing random variations and improving device reliability while maintaining precise threshold voltage control.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If the silicate layer thickness is increased to shift threshold voltage, then Vt control is improved, but the stack thickness increases

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidstack thickness
Core Design Contradiction:
Manufacturing precisionVSLength of stationary object

Solution Approach 1:

The patent combines silicate layers with high dielectric constant materials in a composite structure. This composite approach allows the silicate layer to be kept thin for Vt control while the high dielectric constant material provides the necessary electrical characteristics, achieving both goals without excessive total thickness.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach provides significant shifts in threshold voltage with minimal changes in layer thickness, allowing for the fabrication of multi-Vt devices at smaller sizes with improved manufacturability and reduced resistivity, while avoiding aluminum-related temperature issues.

Implementation Method 1

A high dielectric constant layer is provided on the silicate layer

Methodology Applied
Scientific EffectDielectric: Dielectric

Implementation Method 2

A low temperature anneal is performed after the work function metal layer is provided

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS11476121B2Method of forming multi-threshold voltage devices and devices so formed
Publication Date: 2022.10.18 SAMSUNG ELECTRONICS CO LTD
  • US11476121B2 patent drawing
  • US11476121B2 patent drawing
  • US11476121B2 patent drawing

AI summary

A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.