Silicidation of Bottom Source/Drain Sheet Using Pinch-Off Spacer
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Solution Overview
Problem
The challenge in fabricating vertical field-effect-transistors is the increased resistance due to the distance of the bottom source/drain contact to the transistor, which is exacerbated by the difficulty in silicidation processes at tight fin pitches, leading to defects and device variation.
Innovation Solution
A method is developed to form silicide regions in the bottom source/drain layer, followed by the formation of spacer layers and a gate structure, with additional source/drain layers, to mitigate resistance and prevent metal sticking between fins, ensuring effective contact and reduced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicidation process is applied to bottom source/drain at tight fin pitch, then resistance penalty is mitigated, but metal sticking between fins occurs causing defects and device variation
Solution Approach 1:
The bottom source/drain region is segmented into multiple sections: a first portion that receives silicide formation for low resistance, and a second portion that remains metal-free to prevent sticking defects. This segmentation allows simultaneous achievement of low resistance and defect-free fabrication.
Solution Approach 2:
Different regions of the bottom source/drain are given different properties: the first portion is silicided to reduce resistance, while the second portion is kept metal-free to prevent defects. This local differentiation resolves the contradiction between needing silicide for low resistance and avoiding metal sticking for defect-free manufacturing.
2Reliability
If contact is placed close to transistor to reduce resistance, then resistance penalty is reduced, but fin pitch becomes tighter making silicidation difficult
Solution Approach 1:
The bottom source/drain is divided into a first portion for silicidation and a second portion for contact formation. This segmentation enables close contact placement to the transistor (reducing resistance) while providing a dedicated silicided region that can be formed without metal sticking issues, thus maintaining ease of manufacture.
3Reliability
If silicide is formed in entire bottom source/drain layer, then resistance is reduced, but metal sticking between fins occurs causing defects
Solution Approach 1:
Silicide is formed only in the first portion of the bottom source/drain layer where low resistance is needed, while the second portion remains metal-free to prevent sticking defects. This local quality differentiation eliminates the harmful metal sticking effect while preserving the beneficial low resistance property in the appropriate region.
Solution Approach 2:
The bottom source/drain layer is segmented into a silicided first portion and a non-silicided second portion. This segmentation allows the electrical conductivity to be improved in the first portion without generating metal sticking defects in the second portion.
Data Source
AI summary
A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes at least a substrate, a first source/drain layer, and a plurality of fins each disposed on and in contact with the first source/drain layer. Silicide regions are disposed within a portion of the first source/drain layer. A gate structure is in contact with the plurality of fins, and a second source/drain layer is disposed on the gate structure. The method includes forming silicide in a portion of a first source/drain layer. A first spacer layer is formed in contact with at least the silicide, the first source/drain layer and the plurality of fins. A gate structure is formed in contact with the plurality of fins and the first spacer layer. A second spacer layer is formed in contact with the gate structure and the plurality of fins.