Semiconductor Metal Silicide Formation via Amorphization and Through-Hole Masking
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Solution Overview
Problem
The challenge in fabricating semiconductor elements for integrated circuits lies in forming stable metal silicide layers using the self-aligned silicidation process, as the metal silicide layers formed are prone to damage in high-temperature environments and become increasingly difficult to implement as semiconductor sizes shrink, affecting the performance of metal oxide semiconductors.
Innovation Solution
The method involves an amorphization process followed by a thermal process to form metal silicide layers, where through hole contacts are used as masks for self-aligned silicidation, allowing for the formation of metal silicide layers even with smaller contact diameters, using techniques like pre-amorphization implantation and subsequent thermal reactions to create a stable metal silicide layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-aligned silicidation process is performed to form metal silicide layers, then metal oxide semiconductor circuits can be fabricated, but the metal silicide layers are damaged by high temperature in the high-k gate dielectric formation process
Solution Approach 1:
The patent applies preliminary action by forming the metal silicide layer before the high-k gate dielectric layer formation process. Specifically, the silicidation process is performed at an earlier stage when the structure includes the semiconductor layer, first interlayer insulating layer, and contact holes, but before the high-k gate dielectric is formed. This timing ensures the metal silicide layer is already in place and protected during subsequent high-temperature processing steps.
Solution Approach 2:
The patent implements beforehand cushioning by introducing a protective configuration before high-temperature processing. The metal silicide layer is formed with specific structural characteristics (using particular metal materials and formation methods) that provide inherent thermal stability and protection against damage during the subsequent high-k gate dielectric formation at temperatures of 400°C or higher.
2Manufacturing precision
If through contact self-aligned silicidation process is used, then self-alignment is improved, but the silicidation process becomes difficult to implement as contact diameter decreases
Solution Approach 1:
The patent applies parameter changes by modifying the silicidation process parameters to accommodate smaller contact diameters. The process uses specific metal materials (such as tungsten, molybdenum, or titanium) and controls the silicidation conditions (temperature, time, and reactant exposure) to enable effective silicide formation even in reduced-size contact structures where traditional through-contact self-aligned silicidation becomes difficult.
Solution Approach 2:
The patent replaces the traditional mechanical/chemical silicidation approach with an alternative method that does not rely on reactant intrusion through the contact hole. Instead, the metal silicide layer is formed through deposition and thermal reaction processes that work effectively with smaller contact dimensions, substituting the need for reactant diffusion through the contact structure.
3Productivity
If conventional silicidation process is used, then metal silicide layer can be formed, but additional process steps are required beyond amorphization and thermal processing
Solution Approach 1:
The patent merges multiple process steps into a simplified sequence. The silicidation process is integrated with the amorphization and thermal processing steps, where the metal silicide layer formation is achieved through the combination of amorphization followed by thermal reaction, eliminating the need for separate, complex silicidation工序 and reducing the total number of process steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the successful formation of metal silicide layers in smaller contact diameters, enhancing the performance of metal oxide semiconductors by stabilizing the silicidation process and improving its implementation efficiency.
Implementation Method 1
An amorphization process is performed in the source/drain electrodes to form an amorphous portion
Implementation Method 2
A silicidation process is performed with the through hole contact and the amorphous portion of the source/drain electrodes to form a metal silicide layer
Implementation Method 3
A silicidation process is performed with the through hole contact and the amorphous portion of the source/drain electrodes to form a metal silicide layer
Data Source
AI summary
A fabricating method of a semiconductor element includes the following steps. First, a substrate is provided. A metal gate structure and source/drain electrodes are already formed on the substrate. An amorphization process is performed in the source/drain electrodes to form an amorphous portion. An interlayer dielectric layer is formed on surfaces of the source/drain electrodes and a through hole contact is formed within the interlayer dielectric layer. A silicidation process is performed with the through hole contact and the amorphous portion of the source/drain electrodes to form a metal silicide layer. The fabricating method is capable of finishing the formation of the metal silicide layer in the condition that diameters of the through hole contact is becoming smaller and smaller.