Silicide Block Isolation for RF Switch Off-Capacitance Reduction
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Solution Overview
Problem
Conventional SOI CMOS transistors used in RF switches have high off-capacitance due to overlap regions, which increases power losses and reduces breakdown voltage, making them unsuitable for high-frequency RF applications.
Innovation Solution
A silicide blocking structure is introduced to prevent the formation of metal silicide on channel/body contact regions and polysilicon gate fingers, eliminating overlap capacitance and maintaining high breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional SOI CMOS transistors are used in RF switches, then the transistors can be fabricated using standard CMOS technologies, but the off-capacitance is high due to overlap regions, increasing power losses
Solution Approach 1:
The invention extracts and removes the overlap regions between polysilicon gate fingers and channel/body contact regions, thereby eliminating the source of overlap capacitance. This is achieved by repositioning the channel/body contact regions away from the gate finger overlap areas, directly reducing off-capacitance and associated power losses while maintaining standard CMOS fabrication compatibility
Solution Approach 2:
The invention introduces an intermediary dielectric layer between the polysilicon gate fingers and channel/body contact regions. This dielectric intermediary reduces the capacitive coupling between these structures, thereby reducing off-capacitance without requiring changes to the standard CMOS fabrication process
2Adaptability or versatility
If conventional SOI CMOS transistors are used in RF switches, then the transistors can be integrated into system-on-chip devices, but the high off-capacitance reduces breakdown voltage
Solution Approach 1:
By removing the overlap regions that create high off-capacitance, the invention reduces the electric field concentration at these interfaces. This extraction of problematic overlap structures allows the transistor to sustain higher breakdown voltages while maintaining compatibility with integrated system-on-chip architectures
Solution Approach 2:
The invention applies local quality changes by modifying only the specific overlap regions between gate fingers and contact regions, leaving the rest of the transistor structure intact. This localized modification reduces off-capacitance and improves breakdown voltage without affecting the overall integrability of the device into system-on-chip configurations
Data Source
AI summary
A silicon-on-insulator (SOI) CMOS transistor structure includes a plurality of series-connected SOI CMOS transistors, including a plurality of parallel source/drain regions, a plurality of channel/body regions located between the plurality of source/drain regions, and a polysilicon gate structure located over the plurality of channel regions. The polysilicon gate structure includes a plurality of polysilicon gate fingers, wherein each polysilicon gate finger extends over a corresponding one of the channel/body regions. A silicide blocking structure is formed over portions of the polysilicon gate fingers, wherein channel/body contact regions, which extend at least partially under the silicide blocking structure, provide electrical connections to the parallel channel/body regions.