Silicide Blocking Mask Layout for EOS-Resistant Level Shifters
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Solution Overview
Problem
Semiconductor devices, particularly level shifter blocks in display driver ICs, face failures due to Electrical Overstress (EOS) which can cause damage to the silicide region, leading to current flow issues and line dim failures, as the silicide region's low resistance facilitates excessive current flow to the source region.
Innovation Solution
A mask layout is designed with a silicide blocking region that overlaps the gate electrode and source/drain regions, forming a silicide blocking film to increase resistance and prevent current concentration, thereby reducing the risk of EOS-related failures. This layout includes a body region and protruding regions with specific widths to effectively block current paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicide region is disposed on source region to lower resistance and facilitate current flow, then electrical conductivity is improved, but device becomes vulnerable to EOS damage due to excessive current flow
Solution Approach 1:
The source region is segmented into two distinct zones: a silicide region and a silicide blocking region. The silicide region (first area) provides low resistance for normal current flow, while the silicide blocking region (second area) with higher resistance prevents excessive current during EOS events. This segmentation allows the source region to simultaneously achieve good electrical conductivity and EOS protection.
Solution Approach 2:
Different regions of the source are given different electrical properties. The silicide region has low resistance to facilitate current flow, while the silicide blocking region has high resistance to block excessive current. This local differentiation of electrical properties allows the device to achieve both low on-resistance and EOS protection without compromising overall performance.
2Reliability
If silicide blocking region is added to prevent EOS damage, then device reliability is improved, but manufacturing process complexity increases
Solution Approach 1:
The silicide blocking mask pattern is merged with the gate electrode mask pattern and active mask pattern in the alignment process. By utilizing the existing mask patterns and their alignment relationships, the silicide blocking region is formed without requiring completely independent mask alignment steps, thereby reducing the increase in manufacturing complexity.
Solution Approach 2:
The silicide blocking mask pattern serves multiple functions: it defines the silicide blocking region for EOS protection, and it also serves as a reference for aligning other structures. By making the mask pattern multi-functional, the patent reduces the need for additional dedicated mask steps, thereby limiting the increase in manufacturing process complexity.
Data Source
AI summary
A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.