Silicide Blocking Mask Layout for EOS-Resistant Level Shifters
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices, particularly level shifter blocks in display driver ICs, face failures due to Electrical Overstress (EOS) which can cause damage to the silicide region, leading to current flow issues and line dim failures, as the silicide region's resistance is lower than the gate-drain resistance, making it susceptible to EOS-related failures.
Innovation Solution
A mask layout is designed with a silicide blocking region that overlaps the gate electrode and source/drain regions, forming a silicide blocking film to increase resistance and prevent current flow to the source region during EOS, featuring a body region and protruding regions to disperse EOS current effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicide region is disposed on the source region to lower resistance and help current flow, then the gate-source resistance becomes lower than the gate-drain resistance, but the device becomes susceptible to EOS-related failures due to excessive current flow
Solution Approach 1:
The source region is segmented into two distinct zones: a silicide region and a silicide blocking region. The silicide region (first area) provides low resistance for normal current flow, while the silicide blocking region (second area) with higher resistance prevents excessive current during EOS events. This segmentation allows the source region to simultaneously achieve low resistance operation and EOS protection.
Solution Approach 2:
Different regions of the source region are assigned different electrical properties. The silicide region has low resistance to facilitate current flow during normal operation, while the silicide blocking region has higher resistance to block excessive current during EOS. This local differentiation of electrical properties enables the device to maintain performance while gaining protection.
2Reliability
If the silicide region covers most of the source region to reduce resistance, then current flow is improved, but EOS stress can easily be introduced into the source region causing failure
Solution Approach 1:
The source region is divided into a silicide region and a silicide blocking region. The silicide region covers part of the source region to provide low resistance and stable current flow, while the silicide blocking region covers another part to prevent EOS stress from being easily introduced. This segmentation resolves the contradiction by distributing different functions across different spatial zones.
3Object-affected harmful factors
If a silicide blocking region is designed to reduce current toward the source region during EOS, then EOS resistance is improved, but the device complexity increases due to additional mask patterns and manufacturing steps
Solution Approach 1:
The silicide blocking mask pattern is merged with the gate electrode mask pattern and the active mask pattern in the fabrication process. By aligning and combining these patterns, the silicide blocking region is formed simultaneously with other critical structures, reducing the number of separate manufacturing steps and masks needed while still achieving EOS protection.
Solution Approach 2:
The silicide blocking mask pattern serves multiple functions: it defines the silicide blocking region for EOS protection, aligns with the gate electrode and active regions for proper device formation, and integrates with existing fabrication processes. This multi-functionality reduces overall device complexity despite adding EOS protection capability.
Data Source
AI summary
A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.