Silicide-Blocking Layer for Split Gate Flash Memory
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Solution Overview
Problem
Conventional flash memory fabrication methods are limited by misalignment issues due to precision limitations in photomask technology, leading to manufacturing costs, reduced density, and incompatibility with replacement gate HKMG technology, causing contamination and yield reduction in integrated circuits.
Innovation Solution
A new processing method that forms silicide-blocking materials over the top surfaces of select gates to prevent salicide formation during CMP, ensuring compatibility with replacement gate HKMG technology and reducing contamination, thereby increasing manufacturing yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photomask fabrication methods are used, then manufacturing process is simple, but misalignment occurs leading to reduced manufacturing precision and density
Solution Approach 1:
The patent implements self-aligned fabrication where the select gate structure automatically defines the position of the memory gate and charge trapping layer through conformal deposition and etch processes. The sacrificial layer and spacer structures enable automatic alignment without requiring additional photomask steps, achieving sub-10nm precision without increasing process complexity
Solution Approach 2:
The gate structure is divided into separate select gate and memory gate portions with a charge trapping layer between them. This segmentation allows independent optimization of each gate's function while maintaining precise alignment through the self-aligned fabrication process, eliminating the need for high-precision photomask alignment
2Productivity
If replacement gate HKMG technology is integrated, then device density and performance improve, but metal ion contamination occurs during CMP reducing yield
Solution Approach 1:
The patent introduces a silicide-blocking material as an intermediary layer deposited over the select gate structure before CMP processing. This blocking layer prevents metal ions from the select gate from contaminating the memory gate region during mechanical polishing, enabling safe integration of replacement gate HKMG technology without yield loss
Solution Approach 2:
The silicide-blocking material is applied in advance before the CMP process to prevent contamination. This preliminary protective action stops metal ion migration at the source, allowing the subsequent CMP step to proceed without generating harmful contamination in the memory gate region
Data Source
AI summary
In a method of forming a split gate memory cell, a sacrificial spacer is formed over a semiconductor substrate. A first layer of conductive material is formed over a top surface and sidewalls of the sacrificial spacer. A first etch back process is formed on the first layer of conductive material to expose the top surface of the sacrificial spacer and upper sidewall regions of the sacrificial spacer. A conformal silicide-blocking layer is then formed which extends over the etched back first layer of conductive material and over the top surface of the sacrificial spacer.