Metal-Insulator-Silicide Capacitor Layout for Shorter IC Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The long electrical path between device terminals and metal-insulator-metal (MIM) capacitors in integrated circuits results in high resistance and increased manufacturing costs due to multiple depositions and a large number of masks required for patterning.
Innovation Solution
The use of metal-insulator-silicide structures with a silicide lower electrode reduces resistance and fabrication costs by integrating the silicide directly on the substrate or polysilicon features, thereby minimizing the number of masks needed and shortening the wiring length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal-insulator-metal (MIM) capacitors are integrated into the back-end-of-the-line metal interconnect layers, then decoupling functionality is achieved, but the long electrical path results in high resistance
Solution Approach 1:
The patent transitions from using metal interconnect layers to form capacitor electrodes to using a silicide layer formed directly on the semiconductor substrate. This dimensional change eliminates the need for long vertical and horizontal metal interconnect paths, reducing resistance by placing the capacitor structure at the substrate level rather than in upper metal layers.
Solution Approach 2:
The invention extracts the lower electrode function from the metal interconnect structure and assigns it to a silicide layer formed directly on the substrate. This separation removes the dependency on long metal interconnect paths for establishing the capacitor's lower electrode connection.
2Reliability
If MIM capacitors use multiple metal layers and complex patterning, then capacitor functionality is achieved, but manufacturing costs increase due to multiple depositions and masks
Solution Approach 1:
The patent merges the formation of the silicide layer with existing substrate preparation processes. The silicide layer is formed directly on the semiconductor substrate in a single deposition step, combining multiple functions (substrate preparation and lower electrode formation) into one process, thereby reducing the total number of depositions and masks required.
Solution Approach 2:
The invention changes the material parameter from metal to silicide for the lower electrode, and changes the structural parameter from multi-layer to single-layer configuration. This simplifies the manufacturing process by reducing the number of deposition steps and patterning operations required.
3Reliability
If the electrical path between device terminals and capacitors is lengthened to reach metal interconnect layers, then capacitor integration is achieved, but wiring length increases
Solution Approach 1:
The patent relocates the capacitor structure from upper metal interconnect layers to the substrate level, changing the vertical dimension of capacitor placement. This eliminates the need for long vertical wire runs through multiple metal layers and reduces horizontal wiring length by placing capacitors closer to active devices.
Solution Approach 2:
The silicide layer is formed preliminarily on the substrate before subsequent processing steps. This preliminary formation of the lower electrode structure enables shorter interconnect paths to be used in later stages, as the capacitor is already positioned at the substrate level rather than requiring long paths to reach upper metal layers.
Data Source
AI summary
Some embodiments relate to an integrated circuit including a semiconductor substrate. A silicide structure is disposed over the semiconductor substrate in a cross-sectional view. A dielectric structure is in direct contact with an upper surface of the silicide structure in the cross-sectional view. A metal structure is in direct contact with an upper surface of the dielectric layer in the cross-sectional view, such that the silicide structure and the metal structure establish a bottom electrode and a top electrode, respectively, which are spaced apart from one another by the dielectric structure to establish a metal-insulator-silicide capacitor over the semiconductor substrate.