Silicide-Integrated Common Active Pattern for CMOS Display Transistors
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Solution Overview
Problem
The integration of thin film transistors in display devices, particularly in CMOS configurations, faces challenges due to the need for metal bridges that can cause defects and increase manufacturing costs, as n-doped and p-doped areas do not directly contact each other but are electrically connected through these bridges.
Innovation Solution
A display device with a common active pattern that includes an NMOS area, a PMOS area, and a silicide area in the same layer, electrically connecting the NMOS and PMOS areas without the need for additional bridges, using a silicide area made from materials like titanium silicide, nickel silicide, or tungsten silicide, which contacts the doped areas, and is formed through a process involving polysilicon and silicide metal patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal bridges are used to electrically connect n-doped and p-doped areas in CMOS configuration, then electrical connection is achieved, but manufacturing costs increase and defects are caused due to additional mask processes
Solution Approach 1:
The invention merges the electrical connection function into the active pattern itself by forming a common active pattern that includes both n-doped and p-doped areas in direct contact. This eliminates the need for separate metal bridge structures and additional mask processes, thereby reducing manufacturing costs while maintaining electrical connectivity between different doped regions
Solution Approach 2:
The common active pattern serves multiple functions simultaneously: it acts as both the transistor active region and the electrical connection path between n-doped and p-doped areas. This multi-functional design eliminates the need for dedicated metal bridge structures, simplifying the manufacturing process and reducing the number of process steps
2Reliability
If metal bridges are used to electrically connect n-doped and p-doped areas, then electrical connection is achieved, but transistor damage occurs due to the bridge formation process
Solution Approach 1:
The invention extracts the electrical connection function from the metal bridge structure and integrates it directly into the common active pattern. By removing the need for separate metal bridge formation processes, the harmful effects of bridge formation on transistors are eliminated while maintaining the necessary electrical connectivity
3Reliability
If additional mask is used for forming metal bridges, then electrical connection is achieved, but device complexity increases due to additional process steps
Solution Approach 1:
The invention combines the electrical connection function with the active pattern formation process itself. The common active pattern includes both n-doped and p-doped areas that are in direct contact, eliminating the need for separate metal bridge formation steps and additional masks, thereby reducing overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution eliminates the need for additional bridge patterns, reduces manufacturing costs, and prevents damage to transistors, while increasing the size of the active pattern and capacitance, thereby enhancing the integration and efficiency of display circuits.
Implementation Method 1
a silicide area in a same layer as the NMOS area and the PMOS area and electrically connecting the NMOS area to the PMOS area
Data Source
AI summary
A display device includes a common active pattern, a first gate electrode, and a second gate electrode. The common active pattern includes an NMOS area, a PMOS area, and a silicide area in a same layer as the NMOS area and the PMOS area. The silicide area electrically connects the NMOS area to the PMOS area. The NMOS area includes a first channel area and an n-doped area contacting the first channel area. The PMOS area includes a second channel area and a p-doped area contacting the second channel area. The first gate electrode overlaps the first channel area, and the second gate electrode overlaps the second channel area.