Silicide Conductive Layer for 3D Flash Memory Resistance
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Solution Overview
Problem
The high resistance of polysilicon layers in the fan-out region of 3D stacked flash memory structures leads to delayed programming speed and operational issues, as current ion implantation methods are time-consuming and expensive.
Innovation Solution
A 3D stacked semiconductor structure with alternately arranged oxide and conductive layers, featuring a contact hole with a conductor and insulator, where the conductive layer includes silicide for enhanced conductivity, reducing resistance and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is used to reduce resistance of polysilicon layers, then conductivity is improved, but manufacturing time and cost increase
Solution Approach 1:
The patent changes the material parameter of the conductive layer from pure polysilicon to silicide (such as cobalt silicide, tungsten silicide, or molybdenum silicide). This material parameter change inherently provides lower resistance and higher conductivity without requiring ion implantation processing, thus resolving the contradiction between improving conductivity and reducing manufacturing time.
2Reliability
If ion implantation is used to reduce resistance of polysilicon layers, then conductivity is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the material composition parameter from polysilicon to silicide, which naturally possesses lower resistance. This eliminates the need for expensive ion implantation equipment and processing steps, thereby reducing manufacturing cost while maintaining or improving conductivity.
Solution Approach 2:
The patent employs silicide materials that can be deposited using standard thin-film deposition techniques (such as CVD or sputtering) rather than requiring expensive ion implantation facilities. This substitution with more accessible, cost-effective materials reduces manufacturing cost while achieving the desired electrical performance.
3Volume of moving object
If distance between gates is reduced for size reduction, then device density increases, but junction resistance increases
Solution Approach 1:
The patent changes the material parameter of the conductive layer to silicide, which has inherently lower resistance. This allows the gate distance to be reduced for higher density while maintaining low junction resistance, as the silicide material compensates for the smaller dimensions and prevents resistance increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure achieves lower resistance, increased operational speed, and reduced production costs due to simplified manufacturing processes, resulting in improved performance and efficiency of the 3D flash memory.
Implementation Method 1
the corresponding conductive layer comprises a silicide. The silicide could be formed at edges or an entire body of the corresponding conductive layer
Data Source
AI summary
A three dimensional stacked semiconductor structure comprises a stack including plural oxide layers and conductive layers arranged alternately, at least a contact hole formed vertically to the oxide layers and the conductive layers, and extending to one of the conductive layers, an insulator formed at the sidewall of the contact hole, a conductor formed in the contact hole and connecting the corresponding conductive layer, and the corresponding conductive layer comprises a silicide. The silicide could be formed at edges or an entire body of the corresponding conductive layer. Besides the silicide, the corresponding conductive layer could, partially or completely, further comprise a conductive material connected to the conductor. The corresponding conductive layer which the contact hole extends to has higher conductivity than other conductive layers. Also, the 3D stacked semiconductor structure could be applied to a fan-out region of a 3D flash memory.