Silicide Conductive Layer Design for 3D Memory Substrate Warping
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Solution Overview
Problem
The integration of three-dimensional semiconductor memory devices faces challenges in reducing substrate warping due to thermal expansion coefficient differences between silicon substrates and metal conductive layers, leading to contraction stress and potential device instability.
Innovation Solution
The method involves forming a conductive layer from silicide materials, specifically titanium silicide, which has a smaller thermal expansion coefficient difference with silicon, and using a silicon layer and a second silicide layer to create a crevice for enhanced contact area and reduced electrical resistance, thereby minimizing substrate warping and improving device stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal conductive layers are used in three-dimensional semiconductor memory devices, then electrical conductivity is improved, but substrate warping occurs due to thermal expansion coefficient differences
Solution Approach 1:
The patent employs a composite conductive layer structure consisting of multiple materials with different properties. Specifically, it uses a first conductive layer (e.g., tungsten) providing low electrical resistance, a second conductive layer (e.g., molybdenum) with intermediate thermal expansion coefficient, and a third conductive layer (e.g., titanium nitride) with high thermal expansion coefficient. This composite structure balances electrical conductivity requirements with thermal expansion management to prevent substrate warping.
Solution Approach 2:
The patent changes the thermal expansion parameters of the conductive layer system by selecting materials with progressively different thermal expansion coefficients. The first conductive layer uses a material with low thermal expansion coefficient, the second with intermediate coefficient, and the third with high coefficient. This parameter variation across layers creates a gradient that compensates for thermal stress and prevents substrate warping while maintaining overall electrical conductivity.
2Stability of the object's composition
If silicide materials are used to form conductive layers, then thermal expansion stress is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the conductive layer into multiple distinct silicide layers, each with specific material composition and thickness. The first silicide layer contains titanium silicide, the second silicide layer contains cobalt silicide, and each layer serves a specific function in the stack. This segmentation allows precise control over thermal expansion properties while maintaining a systematic manufacturing approach through defined deposition and annealing processes.
Solution Approach 2:
The patent applies local quality by giving different regions of the conductive layer structure different material compositions and properties. The first silicide layer has specific titanium content optimized for adhesion and low stress, while the second silicide layer has cobalt content optimized for electrical conductivity. Each layer's composition is locally optimized for its specific function within the overall structure, balancing stress management with electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces substrate warping and maintains low electrical resistance, enhancing the stability and performance of three-dimensional semiconductor memory devices by offsetting thermal expansion stresses and increasing contact area for improved conductivity.
Implementation Method 1
reducing substrate warping due to thermal expansion coefficient differences between silicon substrates and metal conductive layers
Implementation Method 2
forming a gate insulating layer and a semiconductor layer on an inner wall of the first opening
Data Source
AI summary
A method of manufacturing a semiconductor memory device according to an embodiment comprises: alternately stacking first inter-layer insulating layers and first layers above a substrate; forming a first opening penetrating the layers stacked above the substrate; and forming a gate insulating layer and a semiconductor layer in the first opening. In addition, the method comprises: forming a second opening penetrating the layers stacked above the substrate; and forming a second inter-layer insulating layer on an inner wall of the second opening. Moreover, the method comprises: forming a first silicide layer and a barrier metal layer on the bottom surface of the second opening; and forming a silicon layer in the second opening such that a crevice is formed in an upper surface of the silicon layer along the second opening. Furthermore, the method comprises: removing part of the silicon layer; and siliciding the silicon layer via the crevice.