Silicide Contacts for IC Density and Resistance
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Solution Overview
Problem
As IC chip density and complexity increase, maintaining adequate electrical connections between silicon features and conductive lines becomes challenging due to reduced contact area, leading to increased contact resistance and issues like silicide encroachment and varying transistor requirements for silicide thickness and resistance.
Innovation Solution
The method involves forming first and second silicide layers with different thicknesses and characteristics on substrate regions with varying pattern densities by using refractory metals like titanium, where the first silicide layer is formed simultaneously with contact hole formation and the second layer is formed in self-aligned contact holes, allowing for tailored contact areas and doping concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase IC chip density, then more components can be packed onto a single chip, but contact area between metal and silicon decreases leading to increased contact resistance
Solution Approach 1:
The patent changes the material parameter from conventional metal to refractory metal (titanium, tungsten, molybdenum, nickel) which forms silicide compounds with silicon. This material parameter change enables formation of highly conductive silicide contacts that maintain low contact resistance even at reduced feature sizes, thus resolving the contradiction between increased chip density and maintained contact reliability
Solution Approach 2:
The patent creates a composite structure by forming silicide compounds (e.g., titanium silicide, tungsten silicide) through thermal reaction between refractory metal and silicon. This composite material approach produces contacts with superior electrical conductivity and reliability compared to pure metal contacts, addressing the contact resistance issue while maintaining small feature sizes
2Ease of manufacture
If uniform silicide formation process is used across all device regions, then process simplicity is maintained, but different transistor types require different silicide thickness and resistance characteristics
Solution Approach 1:
The patent applies local quality by performing selective silicidation on different device regions. First silicide layers are formed on first device regions (e.g., NMOS transistors) and second silicide layers are formed on second device regions (e.g., PMOS transistors) with different thicknesses and characteristics. This allows each transistor type to have optimized contact properties while using a systematic multi-step process that balances complexity with performance requirements
Solution Approach 2:
The patent segments the silicide formation process into distinct stages: forming first silicide layers on first device regions, then forming second silicide layers on second device regions. This segmentation enables independent optimization of silicide characteristics for different transistor types, addressing the need for varied performance characteristics while maintaining a structured manufacturing approach
3Reliability
If thermal treatment is applied to form silicide layer, then conductive contacts are created, but lateral growth of silicide occurs causing encroachment under sidewall spacers and into channel regions
Solution Approach 1:
The patent applies preliminary action by forming a thin conformal metal layer across the entire substrate before selective thermal treatment. This preliminary metal layer formation, followed by controlled thermal processing, allows silicide to form preferentially in contact regions while the conformal nature and controlled conditions limit lateral encroachment under sidewall spacers and into channel regions, thus preventing harmful silicide migration while achieving desired conductivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures reliable and efficient silicide formation, preventing encroachment and leakage current while accommodating different transistor needs by achieving appropriate contact resistance and thickness for diverse silicon features, enhancing the operational performance of IC chips.
Implementation Method 1
thermally treating it to cause the silicon and metal to react and form a silicide layer between the metal and silicon
Implementation Method 2
implanting encroachment-inhibiting ions such as nitrogen into the active regions prior to thermal treatment
Data Source
AI summary
Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.