Metal Silicide Etching for Thin Crystalline Silicon Layers
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Solution Overview
Problem
Current semiconductor device fabrication methods fail to consistently produce thin, uniform, and smooth layers of semiconductor material with thicknesses as low as several hundred nanometers or less, and surface roughness of five nanometers or less, which is essential for advanced semiconductor-on-insulator substrates and 3D integration processes.
Innovation Solution
The method involves forming a metal silicide layer in a portion of the crystalline silicon adjacent to the exposed major surface and selectively etching it using an etchant to achieve the desired thickness and surface smoothness, with the metal silicide being formed through ion implantation or deposition followed by annealing, and then removing it to thin the crystalline silicon layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If conventional methods are used to provide thin layers of semiconductor material, then the layer thickness can be reduced, but the uniformity and surface smoothness deteriorate
Solution Approach 1:
The patent segments the thinning process into multiple stages: first forming a metal silicide layer in a portion of the crystalline silicon, then selectively etching the metal silicide, and finally performing chemical-mechanical polishing (CMP) on the exposed surface. This multi-stage approach allows achieving both thin thickness and high uniformity/smoothness that cannot be obtained by single-step conventional methods
Solution Approach 2:
The patent introduces metal silicide as an intermediary material that facilitates the thinning process. The metal silicide layer is formed adjacent to the exposed major surface, then selectively etched to thin the crystalline silicon layer. This intermediary approach enables precise thickness control and surface smoothness that direct conventional thinning methods cannot achieve
2Length of stationary object
If the layer thickness is reduced to several hundred nanometers or less, then the device integration density improves, but the surface roughness increases
Solution Approach 1:
The patent performs preliminary chemical-mechanical polishing (CMP) on the crystalline silicon layer before forming the metal silicide and etching. This preliminary smoothing action ensures that when the layer is thinned to several hundred nanometers or less, the surface roughness remains at five nanometers or less, preventing the roughness increase that would normally occur with thinning
3Manufacturing precision
If the layer thickness is uniformly controlled within 5% variation, then the device performance improves, but the manufacturing complexity increases
Solution Approach 1:
The patent changes the physical and chemical parameters of the crystalline silicon layer through controlled metal silicide formation and selective etching. By adjusting etchant selectivity, etch time, and CMP parameters, the process achieves uniform thickness control within 5% variation. These parameter changes are systematically managed to improve device performance while keeping the process complexity manageable through standardized semiconductor fabrication techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of semiconductor devices with a final average layer thickness of 500 nm or less and surface roughness of 5 nm or less, enabling the production of high-quality semiconductor-on-insulator substrates and 3D integration structures.
Implementation Method 1
the metal silicide being formed through ion implantation or deposition followed by annealing
Implementation Method 2
the metal silicide being formed through ion implantation or deposition followed by annealing
Implementation Method 3
the metal silicide being formed through ion implantation or deposition followed by annealing
Implementation Method 4
the metal silicide is etched using an etchant selective to the metal silicide relative to the crystalline silicon
Data Source
AI summary
Methods of fabricating semiconductor devices include forming a metal silicide in a portion of a crystalline silicon layer, and etching the metal silicide using an etchant selective to the metal silicide relative to the crystalline silicon to provide a thin crystalline silicon layer. Silicon-on-insulator (SOI) substrates may be formed by providing a layer of crystalline silicon over a base substrate with a dielectric material between the layer of crystalline silicon and the base substrate, and thinning the layer of crystalline silicon by forming a metal silicide layer in a portion of the crystalline silicon, and then etching the metal silicide layer using an etchant selective to the metal silicide layer relative to the crystalline silicon.