Semiconductor Interconnect Structure With Silicide Etch-Stop Interface
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits increases resistance-capacitance (RC) delay time, affecting performance, and existing semiconductor structures have limitations in adhesion and reliability between metal patterns and etch stop layers.
Innovation Solution
Interspersing a metal silicide layer between the metal pattern and the overlying etch stop layer to enhance adhesion and reliability, using a low-temperature plasma self-aligned barrier process to form the metal silicide, and employing a composite etch stop layer with varying dielectric constants to optimize interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but resistance-capacitance (RC) delay time increases and affects integrated circuit performance
Solution Approach 1:
A metal silicide layer is introduced as an intermediary between the metal interconnect and the etch stop layer. This intermediate layer serves as a bridge that improves adhesion and reduces RC delay time, allowing the system to maintain performance despite continued scaling to smaller geometry sizes.
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers including metal interconnect, metal silicide, and etch stop layer. This composite material approach allows optimization of each layer's properties to collectively reduce RC delay while maintaining structural integrity and adhesion during scaling.
2Ease of manufacture
If existing semiconductor structures are used, then manufacturing simplicity is maintained, but adhesion between metal patterns and etch stop layers is insufficient and reliability is compromised
Solution Approach 1:
The metal silicide layer acts as a mediator between the metal pattern and etch stop layer, providing improved adhesion without significantly complicating the manufacturing process. The layer can be formed using standard semiconductor fabrication techniques.
Solution Approach 2:
The patent changes the material parameter by introducing metal silicide with specific physical and chemical properties that enhance adhesion. The low-temperature formation process also represents a parameter change that enables the improvement without requiring extreme processing conditions.
3Reliability
If metal silicide layer is interspersed between metal pattern and etch stop layer, then adhesion and reliability are improved, but device structure becomes more complex
Solution Approach 1:
The patent segments the interface between metal pattern and etch stop layer by inserting a thin metal silicide layer. This segmentation allows each layer to be optimized independently while maintaining overall structural simplicity through the use of thin-film deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves the adhesion between metal patterns and etch stop layers, reducing RC delay and enhancing the time-dependent dielectric breakdown window, while being compatible with existing manufacturing processes.
Implementation Method 1
A surface portion of the metal cap is silicided to form a metal silicide pattern
Implementation Method 2
A surface portion of the metal cap is silicided to form a metal silicide pattern
Data Source
AI summary
A method of forming a semiconductor structure is provided. A first dielectric layer is formed over a substrate. A first metal pattern is formed through the first dielectric layer. A metal cap is formed over the first metal pattern. A surface portion of the metal cap is silicided to form a metal silicide pattern. A composite etch stop layer is formed on the first dielectric layer and the metal silicide pattern. A second dielectric layer is formed on the composite etch stop structure. A second metal pattern is formed through the second dielectric layer and the composite etch stop structure and landed on the metal silicide pattern.