Silicide Extension Substrate Biasing Without Extrinsic Gates

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Solution Overview

Problem

The use of extrinsic gate structures in semiconductor devices increases the overall size and parasitic capacitance, making them less efficient and larger than necessary, while also requiring additional design rule spacing for manufacturing, which complicates the manufacturing process and reduces device performance.

Innovation Solution

Incorporating a silicide material extended between adjacent pick-up gate structures and a doped region that extends into the space between these gates, allowing for reliable bias voltage supply without extrinsic gates, thereby reducing the device size by 13% to 25% and decreasing parasitic capacitance by 13%, leading to faster operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If extrinsic gate structures are added to gate structures to pick up bias voltage, then the bias voltage control capability is improved, but the device size increases by 13% to 25%

Engineering Contradiction:
Improvebias voltage control capabilityVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the extrinsic gate structure from the gate structure and replaces it with a separate pick-up gate structure. This separation allows the bias voltage to be picked up independently without requiring additional extrinsic gate extensions, thereby reducing the overall device size while maintaining bias voltage control capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the gate structure into intrinsic gate portions and adds separate pick-up gate structures. This segmentation allows the bias voltage pickup function to be performed by dedicated structures rather than expanding the main gate, thus reducing the area occupied by the gate structure while maintaining the ability to control threshold voltage.

Inventive Principle:
Principle #1Segmentation

2Reliability

If extrinsic gate structures are added to gate structures to pick up bias voltage, then the bias voltage control capability is improved, but the parasitic capacitance increases by 13%

Engineering Contradiction:
Improvebias voltage control capabilityVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the bias voltage pickup function from the extrinsic gate and implements it through separate pick-up gate structures. This separation reduces the overlapping area between gate structures and conductive regions, thereby decreasing parasitic capacitance while maintaining the ability to pick up bias voltage.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If extrinsic gate structures are added to gate structures, then the bias voltage pickup capability is improved, but the manufacturing complexity increases due to additional design rule spacing requirements

Engineering Contradiction:
Improvebias voltage pickup capabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the gate structure into intrinsic gates and adds separate pick-up gates with simplified geometries. This segmentation allows for easier manufacturing as the pick-up gates have simpler shapes that are more compatible with standard fabrication processes and design rules, reducing manufacturing complexity while maintaining bias voltage pickup capability.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240055500A1Method of using semiconductor device and method of making
Publication Date: 2024.02.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240055500A1 patent drawing
  • US20240055500A1 patent drawing
  • US20240055500A1 patent drawing

AI summary

A method of biasing a substrate includes electrically connecting a silicide structure to a bias voltage supply. The method further includes conducting a bias voltage received by the silicide structure to a silicide extension extending from a main body of the silicide structure, wherein the silicide extension extends between adjacent gate structures of a plurality of first gate structures. The method further includes transferring the bias voltage from the silicide extension into a doped region of a substrate below the adjacent gate structures of the plurality of first gate structures.