Silicide Gate Fill Structure for Precise Nanosheet Gate Metal Etching

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Solution Overview

Problem

In semiconductor fabrication, there is a challenge in ensuring the proper formation of thin gate metal layers in gate all around nanosheet transistors, which affects the resistance and threshold voltages of integrated circuits, leading to performance issues and increased wafer scrap rates.

Innovation Solution

The use of machine learning techniques to control etching processes for forming gate all around nanosheet transistors, allowing for the selective inclusion or exclusion of thin gate metal layers and precise etching of these layers to achieve low resistance and varying threshold voltages, ensuring the gate fill material can fill more of the trench effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If thin-film deposition and etching techniques are used to decrease feature size, then the number of transistors per area increases, but the proper formation of thin gate metal layers becomes difficult to ensure

Engineering Contradiction:
Improvenumber of transistors per areaVSAvoidproper formation of thin gate metal layers
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent modifies etching process parameters including using a multi-step etching sequence with different chemistries (CHF3, CF4, C4F8), adjusting pressure, temperature, and gas flow rates to achieve precise control over thin gate metal layer formation while maintaining high transistor density

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies preliminary actions by forming a sacrificial layer and using self-aligned spacer formation before the actual gate metal deposition, ensuring proper trench definition and alignment prior to thin gate metal layer formation, which prevents formation defects

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If machine learning techniques are applied to control etching processes, then manufacturing precision of thin gate metal layers improves, but process complexity increases

Engineering Contradiction:
Improveetching precision of thin gate metal layersVSAvoidprocess control complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent implements feedback control by using in-situ monitoring during etching processes and applying machine learning algorithms that analyze real-time process data to dynamically adjust etching parameters, ensuring precise thin gate metal layer formation while the system self-optimizes

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent replaces traditional mechanical/manual process control with machine learning-based automated control systems that use computational algorithms to manage etching parameters, reducing human intervention while improving precision

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12183787B2Semiconductor device with silicide gate fill structure
Publication Date: 2024.12.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12183787B2 patent drawing
  • US12183787B2 patent drawing
  • US12183787B2 patent drawing

AI summary

A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process.