Silicided Gate Spacer Recess Etch for Sub-50nm Uniformity
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Solution Overview
Problem
Current methods struggle to form uniform silicide layers on polysilicon gates with dimensions below 50 nm, leading to voiding and spiking issues, and existing overetch techniques result in incremental reductions and degraded electrical properties.
Innovation Solution
A method involving multiple recess etches to expose additional gate surface area for silicidation, decoupling implant region location from spacer dimensions and final gate surface area, allowing for increased silicide formation without affecting electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If polysilicon gate length is reduced to below 50 nm, then device scaling is achieved, but uniform silicide layer formation becomes impossible due to voiding and spiking
Solution Approach 1:
The spacer recess etch process is divided into multiple sequential etch steps rather than a single overetch step. This segmentation allows precise control over the exposed gate surface area, enabling uniform silicide formation on sub-50nm gates while maintaining accurate implant region definition. Each etch step can be independently optimized to achieve the desired gate exposure without the degradation effects of extensive single-step overetching.
2Manufacturing precision
If overetching of spacer structures is employed to expose additional gate surface area, then silicide film uniformity improves, but electrical properties degrade rapidly
Solution Approach 1:
The implant regions are defined at an intermediate stage during the multi-step spacer recess etch process, before the final gate surface area is fully exposed. This preliminary action decouples the implant region definition from the final gate exposure extent, allowing the process to achieve both adequate gate surface area for uniform silicide and proper implant region positioning for maintained electrical properties.
Solution Approach 2:
The etch process is segmented into multiple steps with implant region definition occurring at an intermediate step. This allows the first etch steps to expose sufficient gate surface area for uniform silicide formation, while subsequent steps complete the gate exposure without further affecting implant region positioning, thus preserving electrical properties.
3Manufacturing precision
If extensive overetching is used to increase gate surface area, then more uniform silicide films can be formed, but the reduction in achievable gate length becomes incremental at best
Solution Approach 1:
Implant regions are defined at an intermediate etch stage, which establishes fixed reference points that enable subsequent etch steps to aggressively expose gate surface area without compromising device functionality. This preliminary definition allows maximum gate length reduction while ensuring adequate silicide formation surface area.
Solution Approach 2:
The multi-step etch process with intermediate implant definition allows each subsequent etch step to focus solely on maximizing gate exposure. Since implant regions are already defined, later steps can remove more spacer material to expose additional gate surface area, thereby achieving greater gate length reduction while maintaining silicide uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reproducible formation of uniform silicide layers on reduced polysilicon gates, reducing polysilicon line resistance, increasing device speed, and relaxing overlay requirements while preventing voiding and maintaining electrical performance.
Implementation Method 1
The structure is subjected to a first etch which exposes a first lateral portion of the gate... The structure is then subjected to a second etch which exposes a second lateral portion of the gate
Implementation Method 2
An implant region is created in a portion of the substrate adjacent to the spacer
Implementation Method 3
the first and second lateral portions of the gate are silicided
Data Source
AI summary
A method is provided for making a silicided gate (209). In accordance with the method, a semiconductor structure (201) is provided which comprises a semiconductor substrate (202), a gate (209) disposed on the semiconductor substrate, and a spacer (219) adjacent to the gate. The structure is subjected to a first etch which exposes a first lateral portion of the gate. An implant (215) is then created in a region adjacent to the spacer. The structure is then subjected to a second etch which exposes a second lateral portion of the gate electrode, and a layer of silicide (225) is formed which extends over the first and second lateral portions of the gate.