Silicide-Protected Interconnection Structure for Via Misalignment
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Solution Overview
Problem
The semiconductor industry faces challenges with via misalignment in small pitches (<20 nm), leading to reliability issues in interconnection structures due to high capacitance and resistance, especially with larger barrier portions in trenches and high ESL of metal oxide.
Innovation Solution
The proposed solution involves a method for manufacturing an interconnection structure that includes forming a first conductive feature on a dielectric layer, followed by the deposition of a barrier layer and a second dielectric layer. A planarization process is performed to expose the top surface of the conductive feature, and a silicide layer is formed using rapid atomic layer deposition to surround the capping layer, enhancing the structure's reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch is reduced to increase integration density, then more components can be integrated into a given area, but via misalignment issues occur leading to reliability degradation
Solution Approach 1:
A silicide layer is formed on the conductive feature before the trench formation process. This preliminary silicide layer acts as a buffer that compensates for alignment variations, ensuring reliable electrical connection even when via placement deviates from ideal positions due to reduced pitch dimensions
Solution Approach 2:
The interconnection structure uses a composite approach by combining silicide material with the conductive feature before trench formation. This composite structure provides both electrical conductivity and mechanical robustness, allowing the via to maintain reliable connection despite misalignment in small pitch configurations
2Reliability
If a larger barrier portion is used in the trench, then resistance is reduced, but capacitance increases due to high ESL of metal oxide
Solution Approach 1:
The invention changes the material parameter of the barrier layer by using silicide material with optimized thickness and composition. This parameter optimization allows the barrier to provide low resistance while the surrounding low-k dielectric material compensates for capacitance effects, achieving both low resistance and low capacitance simultaneously
3Productivity
If the dimensions of conductive features are reduced, then integration density increases, but manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The silicide layer is deposited on the conductive feature before trench formation and patterning. This preliminary silicide coating provides a well-defined interface and material contrast that enhances the precision of subsequent lithography and etching processes, enabling better dimensional control even at reduced feature sizes
Solution Approach 2:
The silicide layer is selectively formed only on the conductive feature surface, providing localized material properties that enhance manufacturing precision. This local modification creates distinct etch selectivity and surface characteristics that improve the accuracy of subsequent processing steps without affecting the entire structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of interconnection structures by reducing via misalignment issues, minimizing capacitance and resistance, and providing a robust silicide layer that protects against misalignment, especially in small pitch configurations.
Implementation Method 1
a silicide layer is formed using rapid atomic layer deposition to surround the capping layer
Data Source
AI summary
An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.