Silicide Layer Selection for DRAM Logic Transistors
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Solution Overview
Problem
Conventional semiconductor devices with nickel silicide layers face challenges in reducing source/drain region resistance and junction leakage, particularly in embedded DRAM devices with short gate lengths, leading to potential current leaks and operational speed limitations.
Innovation Solution
A semiconductor device design featuring separate regions with cobalt or titanium silicide layers on source/drain and gate electrodes of first transistors and nickel-containing silicide layers on second transistors, allowing for independent choice of silicide types based on region characteristics to balance performance and production yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If nickel silicide layer is formed on source/drain regions and gate electrodes of transistors in DRAM section, then operation speed is improved, but junction leakage current increases
Solution Approach 1:
The patent applies different silicide materials to different regions of the semiconductor device. Specifically, nickel silicide is formed on transistors in the logic section where high-speed operation is critical, while cobalt silicide or titanium silicide is formed on transistors in the DRAM cell section where low junction leakage is paramount. This spatial differentiation of material properties resolves the contradiction by allowing each region to optimize for its primary performance requirement.
Solution Approach 2:
The semiconductor device is segmented into functionally distinct regions (DRAM cell section and logic section) with different silicide configurations. The patent divides the transistor population into two groups based on their functional requirements, applying nickel silicide to logic transistors for speed and cobalt/titanium silicide to DRAM transistors for reliability. This segmentation allows simultaneous optimization of both speed and leakage performance across the device.
2Speed
If nickel silicide layer is formed to reduce source/drain region resistance, then operation speed improves, but manufacturing complexity increases due to selective formation processes
Solution Approach 1:
The patent uses insulating films as preliminary protective layers that are selectively removed before silicide formation. First, a first insulating film is formed and selectively removed in the DRAM region, then a second insulating film is formed and selectively removed in the logic region. This preliminary selective removal sequence enables subsequent selective silicide deposition without requiring complex in-situ patterning, simplifying the overall manufacturing process while achieving the desired spatial differentiation.
Solution Approach 2:
The patent introduces insulating films as intermediary layers that facilitate selective silicide formation. These intermediary films are deposited over the entire surface, then selectively removed in specific regions to expose underlying structures for silicide formation. This intermediary approach simplifies the process by using a uniform deposition step followed by selective removal, rather than requiring complex selective deposition techniques.
3Reliability
If cobalt silicide or titanium silicide is used in DRAM section, then junction leakage is suppressed, but source/drain region resistance increases compared to nickel silicide
Solution Approach 1:
The patent recognizes that different regions have different primary requirements: DRAM transistors prioritize low junction leakage over low resistance, while logic transistors prioritize low resistance for high-speed operation. By applying cobalt silicide or titanium silicide specifically to DRAM transistors and nickel silicide to logic transistors, the patent allows each region to have optimized material properties matching its functional needs, resolving the contradiction between leakage suppression and resistance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability and production yield of semiconductor devices by using thermally stable silicides in critical regions and nickel silicide for enhanced operation speed in smaller transistors, effectively managing junction leakage and resistance.
Implementation Method 1
Nickel atoms in the nickel silicide layer are more likely to diffuse across p-n junctions at the source/drain interfaces into the silicon substrate during annealing involved in the process of manufacturing
Implementation Method 2
annealing them at a first temperature, to thereby form a first silicide layer on said first source/drain regions and on said first gate electrodes
Data Source
AI summary
In one embodiment of the present invention, provided is a semiconductor device having a silicon substrate provided with a DRAM region containing first transistors and capacitor elements, and with a logic region containing second transistors. A minimum gate length of the second transistors provided in the logic region is smaller than a minimum gate length of the first transistors provided in the DRAM region. One of a cobalt silicide layer and a titanium silicide layer is provided on source/drain regions and on gate electrodes of the first transistors provided in the DRAM region, and a nickel-containing silicide layer is provided on source/drain regions and on gate electrodes of the second transistors provided in the logic region.