Metal Silicide Memory Contacts With Taller Epitaxial Plugs
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Solution Overview
Problem
As electronic device features shrink, contact resistance increases due to smaller dimensions and reduced spacing, and conventional methods like epitaxial growth and implant processes are self-limiting and damage-prone, limiting the integration density and performance of memory devices like DRAM.
Innovation Solution
A method involving the formation of a contact structure using epitaxially grown monocrystalline silicon, a crystalline material, and metal silicide, where the crystalline material is directly formed over the monocrystalline silicon, increasing the epitaxial plug thickness and reducing contact resistance without the need for an implant process, and the process conditions are varied to form both materials in a single continuous process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature dimensions are reduced to increase integration density, then integration density improves, but contact resistance increases
Solution Approach 1:
The patent changes the physical and chemical parameters of the contact structure by forming a crystalline material layer with specific crystallographic orientation (e.g., <110> or <100>) over the monocrystalline silicon, and controlling the thickness and composition of the metal silicide layer, to reduce contact resistance while maintaining small feature dimensions
Solution Approach 2:
The patent employs a composite contact structure consisting of multiple materials: monocrystalline silicon, crystalline material (such as silicon germanium), and metal silicide, where each material contributes specific properties to achieve low contact resistance in scaled devices
2Manufacturing precision
If epitaxial growth is used to form monocrystalline silicon in constrained regions, then monocrystalline silicon is formed, but the process is self-limiting and cannot achieve sufficient thickness
Solution Approach 1:
The patent segments the contact structure into multiple functional layers: a monocrystalline silicon base layer formed by epitaxial growth, and an additional crystalline material layer formed by subsequent deposition or growth, allowing each layer to contribute to the overall thickness and functionality
Solution Approach 2:
The patent introduces a crystalline material layer as an intermediary between the monocrystalline silicon and the metal silicide, which facilitates continued growth and achieves the required thickness while maintaining crystal quality
3Ease of manufacture
If implant process is used to form amorphous silicon interface, then amorphous silicon is formed, but contact resistance increases due to damage
Solution Approach 1:
The patent extracts or eliminates the implant process step from the manufacturing sequence, replacing it with alternative methods such as direct epitaxial growth or chemical vapor deposition to form the amorphous silicon interface without introducing damage that would increase contact resistance
Solution Approach 2:
The patent replaces the mechanical implant process with a chemical deposition or growth process to form the amorphous silicon interface, substituting a damaging physical method with a gentler chemical method that avoids contact resistance issues
4Manufacturing precision
If multiple separate processes are used to form crystalline material and metal silicide, then each material is formed with control, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of the crystalline material layer and the metal silicide layer into a single integrated process step or closely coupled sequence, where both materials are deposited or grown together or in immediate succession, reducing the number of separate process modules required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance and enhances the integration density of memory devices by increasing the epitaxial plug height, improving electrical conductivity and thermal stability while simplifying manufacturing processes and reducing costs.
Implementation Method 1
a monocrystalline semiconductor material (e.g., a monocrystalline silicon material) selectively epitaxially grown over the access device
Data Source
AI summary
An apparatus comprises a memory array comprising access lines, digit lines, and memory cells. Each memory cell is coupled to an associated access line and an associated digit line and each memory cell comprises an access device, and a monocrystalline semiconductor material adjacent to the access device. A width of the monocrystalline semiconductor material is within a range of from about 8 nm to about 25 nm. Each memory cell comprises a metal silicide material over the monocrystalline semiconductor material, a metal contact material over the metal silicide material, and a storage node adjacent to the metal contact material. Methods of forming an apparatus and systems are also disclosed.