Silicide Memory Pillar Schottky Junction Erase Speed
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in erase operations due to weak electric fields at junction interfaces, leading to insufficient erasure characteristics and prolonged erase times.
Innovation Solution
The implementation of a memory pillar structure with a silicide layer in contact with a semiconductor layer, forming a Schottky diode junction, which increases the electric field and GIDL current, improving erasure characteristics by using NiSi2 as the silicide layer and non-doped monocrystal silicon as the semiconductor layer, and employing metal-induced lateral crystallization (MILC) to form monocrystal silicon channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory pillar structure is used, then manufacturing is simpler, but erasure characteristics are insufficient due to weak electric field at junction interface
Solution Approach 1:
The patent changes the material parameters at the junction interface by forming a silicide layer (such as NiSi2) in contact with the semiconductor layer. This material parameter change creates a Schottky diode junction with superior electric field characteristics compared to conventional structures, thereby improving erasure characteristics without fundamentally changing the overall memory pillar architecture.
Solution Approach 2:
The patent employs a composite structure at the junction interface by combining silicide material with semiconductor material to form a Schottky diode junction. This composite material approach creates a junction with enhanced electric field properties that improves erasure characteristics while maintaining structural integration with the existing memory pillar.
2Reliability
If more erase pulses are applied, then erasure completeness improves, but erase time increases
Solution Approach 1:
The silicide layer changes the electrical parameters at the junction interface, creating a Schottky diode with enhanced GIDL current generation. This parameter change enables more effective charge removal during erase operations, achieving complete erasure with fewer pulse applications and thereby reducing total erase time.
3Power
If silicide layer is added to form Schottky diode junction, then GIDL current and electric field increase, but manufacturing process becomes more complex
Solution Approach 1:
The patent achieves enhanced GIDL current by changing the material parameter at the junction through silicide formation. This can be accomplished by modifying existing deposition or annealing processes to form the silicide layer, rather than adding entirely new process steps, thereby improving power characteristics while minimizing manufacturing complexity increases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances erasure efficiency by increasing the GIDL current, reducing the number of erase pulse applications, and shortening erase times, while also lowering channel resistance and contact resistance.
Implementation Method 1
a memory pillar structure with a silicide layer in contact with a semiconductor layer, forming a Schottky diode junction, which increases the electric field and GIDL current
Implementation Method 2
increases the electric field and GIDL current, improving erasure characteristics
Implementation Method 3
employing metal-induced lateral crystallization (MILC) to form monocrystal silicon channels
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first interconnect layer, a first insulating layer, a second interconnect layer, and a memory pillar including a second insulating layer, a charge storage layer, and a third insulating layer stacked on a part of a side surface and on the bottom surface of the memory pillar, and a first silicide layer in contact with the first interconnect layer, a semiconductor layer, and a second silicide layer stacked in order along a first direction. A height position of a bottom surface of the first silicide layer is lower than a top surface of the first interconnect layer, and a height position of a top surface of the first silicide layer is higher than a bottom surface of the second interconnect layer.