Source/Drain Contact Liner Formation Without Silicide Coverage
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) scale down beyond 32 nm, increased source/drain contact resistance and reduced isolation between nearby contacts become significant challenges, necessitating effective methods to reduce contact resistance and maintain isolation.
Innovation Solution
A process involving the selective deposition of an organic inhibitor on source/drain silicidation exposed in contact holes, followed by forming a dielectric liner layer on the sidewalls without covering the inhibitor, which avoids vertical etching and increases the source/drain contact area, thereby reducing resistance and improving isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation methods are used, then fabrication process is simpler, but source/drain contact resistance increases and isolation between contacts deteriorates
Solution Approach 1:
The method performs preliminary actions by depositing the dielectric liner layer on the sidewalls before removing the inhibitor, and by pre-forming the inhibitor pattern on the silicidation surface. This preliminary structuring enables subsequent self-aligned contact hole formation and metal filling, achieving low resistance and good isolation without requiring complex post-processing alignment steps.
Solution Approach 2:
The organic inhibitor layer serves as an intermediary that temporarily occupies the contact hole bottom area, preventing dielectric liner deposition there while allowing liner formation on sidewalls. This intermediary structure enables precise control of contact geometry and facilitates self-aligned processing, reducing both contact resistance and improving isolation without increasing overall process complexity.
2Ease of manufacture
If vertical etching of dielectric liner is performed, then contact hole formation is complete, but source/drain contact area is reduced and resistance increases
Solution Approach 1:
The inhibitor is pre-deposited on the silicidation surface before contact hole etching, establishing a protective mask that prevents dielectric liner deposition on the contact bottom. This preliminary action ensures that when contact holes are formed and filled, the full contact area is available for metal deposition, minimizing contact resistance while the sidewall liner provides necessary isolation.
Solution Approach 2:
The inhibitor performs a preliminary anti-action by preventing dielectric liner material from depositing on the contact hole bottom area where it would otherwise block metal contact. This preemptive protection occurs during the liner deposition step, eliminating the need for subsequent removal steps that would reduce contact area and increase resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances process robustness, reduces source/drain contact resistance, and maintains good isolation between contacts and gates, improving overall IC performance.
Implementation Method 1
selectively depositing an inhibitor on the silicide feature, wherein the inhibitor is not deposited on surfaces of the contact etch stop layer
Implementation Method 2
The inhibitor includes an organic film having amphiphilic molecules
Data Source
AI summary
A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.