Silicide Layer Pull-Back for Flash Memory Leakage Control
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Solution Overview
Problem
Flash memory devices formed using existing technology have relatively low stability and poor reliability due to reduced distance between adjacent memory cells, leading to breakdown voltage issues and leakage currents during electrical connections.
Innovation Solution
A method involving a pull-back process to reduce the size of the silicide layer parallel to the substrate surface, increasing the distance between the silicide layer and conductive structures, thereby enhancing breakdown voltage and preventing leakage currents, which includes forming a silicide layer in the control gate layer, reducing its resistance, and using dielectric layers for electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the distance between adjacent memory cells is reduced to increase integration density, then the area per memory cell is reduced, but the breakdown voltage decreases and leakage currents increase
Solution Approach 1:
The patent introduces a vertical dimension by forming a raised dielectric layer that elevates the conductive structure above the surrounding planar surface. This vertical separation (height difference) increases the effective distance between adjacent memory cells without reducing their planar footprint, thereby maintaining breakdown voltage while preserving high integration density.
Solution Approach 2:
The raised dielectric layer acts as an intermediary structure between adjacent memory cells. It provides physical and electrical isolation through its elevated position and greater thickness, preventing direct interaction between conductive structures of neighboring cells that would otherwise occur at reduced planar spacing.
2Loss of energy
If a metal silicide layer is formed in the control gate layer to reduce resistance, then the electrical conductivity is improved, but the stability and reliability deteriorate due to leakage currents
Solution Approach 1:
The patent selectively removes portions of the metal silicide layer through pull-back processes to create gaps or discontinuities. This extraction eliminates direct conductive paths that would cause leakage between control gates of adjacent memory cells, while retaining sufficient silicide material to maintain low resistance within each individual control gate.
Solution Approach 2:
The continuous metal silicide layer is segmented into discrete portions by removing intermediate sections. This segmentation prevents lateral leakage currents between adjacent memory cells while preserving the low-resistance electrical connection within each control gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the stability and reliability of flash memory devices by increasing breakdown voltage and preventing leakage currents, resulting in enhanced performance and reliability.
Implementation Method 1
a metal silicide layer 115 is formed in the control gate layer 113 using a self-aligned silicide process to reduce the resistance of the control gate layer 113
Implementation Method 2
a fourth dielectric layer can be formed on the substrate and on the memory cell... The fourth dielectric layer can have a top surface higher than a top surface of the memory cell
Data Source
AI summary
Memory devices are provided. A memory device includes one or more adjacent memory cells on a substrate. A memory cell includes first dielectric layer on the substrate, floating gate, second dielectric layer, control gate layer, and first mask layer. The control gate layer has a first portion and a second portion thereon. A silicide layer is in the control gate layer and covers at least a sidewall of the second portion of the control gate layer. In a direction parallel to a surface of the substrate, the silicide layer has a size smaller than the first portion of the control gate layer or a size of the floating gate layer. A fourth dielectric layer is on the substrate and on the memory cell. The fourth dielectric layer contains an opening exposing a portion of the substrate between adjacent memory cells. A conductive structure is in the opening.