Silicide Formation With Reduced Sidewall Spacers
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Solution Overview
Problem
As integrated circuits scale, the reduced space between transistor gates leads to poorly formed silicide due to narrow sidewall spacers, resulting in higher contact resistance and degraded transistor performance.
Innovation Solution
A process is developed to form integrated circuits with reduced sidewall spacers by etching the sidewall dielectric and removing the etch stop layer self-aligned to the spacers, allowing for improved silicide formation and reduced series resistance, which involves implanting source and drain dopants and forming silicide in a controlled manner to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sidewall spacers are used to provide sufficient distance between transistor channel and deep source drain, then short channel effects are avoided, but the space between sidewall spacers on adjacent transistors becomes too small to form high quality silicide
Solution Approach 1:
The patent applies partial action by selectively removing portions of the sidewall spacers only in the regions where contacts are to be formed, while maintaining the full sidewall spacer structure in other regions. This selective removal creates enlarged silicide formation areas locally without compromising the overall transistor structure and short channel effect prevention.
Solution Approach 2:
The patent implements local quality by creating different sidewall spacer configurations in different regions: full-height sidewall spacers in transistor regions and reduced-height sidewall spacers in contact regions. This allows high-quality silicide formation in contact areas while maintaining proper transistor operation in channel areas.
2Manufacturing precision
If sidewall spacers are reduced to enable improved silicide formation, then contact resistance is reduced, but the space between transistors must be carefully managed
Solution Approach 1:
The patent segments the sidewall spacer structure into multiple height levels: full-height sidewall spacers for transistor isolation and reduced-height sidewall spacers for contact formation. This segmentation allows simultaneous achievement of good silicide formation and transistor performance by assigning different functions to different segments of the sidewall spacer structure.
3Ease of manufacture
If contact etch is performed, then contact holes are formed, but the etch may etch away a portion of the sidewalls causing the contact to land on unsilicided active area
Solution Approach 1:
The patent applies beforehand cushioning by forming silicide on the active area before performing the contact etch. The silicide layer acts as a protective cushion that prevents the contact etch from exposing the unsilicided active area, ensuring that even if the etch removes some sidewall material, the contact will still land on silicided material and maintain low contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower sheet resistance and improved contact resistance, enhancing the performance of transistors operating in series, such as NAND gates, by creating a good silicide formation area with reduced sidewall spacers and minimizing substrate damage.
Implementation Method 1
implanting source and drain dopants self aligned to the sidewall spacers
Data Source
AI summary
A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching a sidewall dielectric and stopping on an etch stop layer, implanting source and drain dopants self aligned to the sidewall spacers, followed by removing a portion of the sidewall dielectric and removing the etch stop layer self aligned to the reduced sidewall spacers prior to forming silicide.