Multi-Tiered Semiconductor Voids via Silicide Sacrificial Templates

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Solution Overview

Problem

The formation of multi-tiered semiconductor devices is costly due to difficulties in creating features in multiple layers of semiconductor material, and existing methods lack control over the formation of uniform voids within these structures.

Innovation Solution

The process involves depositing metal on tiers of dielectric material interleaved with semiconductor material, annealing to form metal silicide, substantially removing the metal, and further processing to create controlled, uniform voids where devices like floating gates can be formed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional methods are used to form features in multiple layers of semiconductor material, then device functionality is achieved, but manufacturing cost increases and control over uniform void formation is lost

Engineering Contradiction:
Improvecontrol over uniform void formationVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by depositing metal layers and forming silicide structures before creating the final voids. The metal is deposited on dielectric tiers, annealed to form silicide, and then removed to create uniformly controlled voids. This preliminary formation of silicide structures provides a template that ensures uniform void formation throughout the multi-tiered structure, solving the control problem while maintaining cost-effectiveness through standardized processing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses metal silicide as an intermediary material to achieve uniform void formation. The metal layer is deposited, converted to silicide through annealing, and then removed. This intermediary silicide phase acts as a sacrificial structure that ensures uniform void creation across multiple tiers. The silicide formation process provides the necessary control mechanism, while the subsequent removal creates the desired voids without requiring complex direct void formation techniques.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If metal is deposited and annealed to form silicide in multi-tiered structures, then uniform voids can be created, but process complexity increases

Engineering Contradiction:
Improveuniform void formationVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the void formation process into distinct stages: metal deposition, silicide formation through annealing, and metal removal. Each stage is independently controlled and optimized. The segmentation allows for precise control of void formation by breaking down the complex process into manageable steps, where each step contributes to the overall uniformity of the final void structure without requiring the entire process to be optimized simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent utilizes parameter changes, specifically temperature variation during annealing, to control silicide formation. By adjusting the annealing temperature and duration, the metal converts to silicide with controlled morphology and distribution. This parameter control provides a simple yet effective mechanism to achieve uniform void formation without introducing complex process equipment or procedures, maintaining relative process simplicity while achieving high precision.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method allows for the controlled formation of substantially uniform voids in semiconductor material, facilitating the creation of semiconductor devices with improved precision and cost-effectiveness.

Implementation Method 1

The metal film can be annealed to cause the metal inside the vertical channel to react with the tiers of polysilicon to form portions of silicide

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 2

the metal inside the vertical channel to react with the tiers of polysilicon to form portions of silicide

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Data Source

PatentUS8872252B2Multi-tiered semiconductor apparatuses including residual silicide in semiconductor tier
Publication Date: 2014.10.28 MICRON TECHNOLOGY INC
  • US8872252B2 patent drawing
  • US8872252B2 patent drawing
  • US8872252B2 patent drawing

AI summary

Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.