Silicide Source-Drain Layout Close to the Transistor Channel
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Solution Overview
Problem
Existing methods for forming metal-semiconductor alloy regions in transistors lack precise control over the interfaces between the metal-semiconductor alloy regions and the crystalline semiconductor channel zone, leading to potential issues with contact quality and thermal budget in 3D device manufacturing.
Innovation Solution
A method involving amorphization of semiconductor regions on either side of the transistor gate, followed by selective formation of metal-semiconductor alloy regions in these amorphous areas, allowing for precise positioning and reduced thermal budget, with optional doping and activation annealing to maintain amorphous regions without recrystallization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal-semiconductor alloy regions are formed close to the channel in the same surface layer, then contact quality and positioning precision are improved, but the interface control between alloy regions and crystalline channel zone becomes difficult
Solution Approach 1:
The surface semiconductor layer is divided into two distinct regions: amorphous semiconductor regions for forming metal-semiconductor alloy contacts and a crystalline semiconductor zone for the channel. This segmentation allows each region to have optimized properties - the amorphous regions enable precise alloy formation close to the channel, while the crystalline zone maintains channel performance, thus resolving the interface control issue.
Solution Approach 2:
Different crystallographic qualities are applied to different parts of the surface semiconductor layer. The amorphous regions provide localized suitability for metal-semiconductor alloy formation with precise interface control, while the crystalline zone provides suitable properties for channel operation. This local quality differentiation enables both close positioning and reliable interface control.
2Reliability
If epitaxial growth is used to form raised source and drain zones, then contact quality is improved, but manufacturing cost and thermal budget increase
Solution Approach 1:
The patent changes the physical state parameter of the semiconductor material from crystalline to amorphous in the source and drain regions. This parameter change enables metal-semiconductor alloy formation at lower temperatures without requiring epitaxial growth, thus reducing the thermal budget while maintaining good contact quality through the alloy regions.
3Reliability
If multiple processing steps including epitaxial growth are used, then contact quality is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the epitaxial growth step from the manufacturing process. By forming metal-semiconductor alloy regions directly in amorphous semiconductor regions, the complex multi-step epitaxial process is eliminated, reducing device complexity and manufacturing cost while maintaining contact quality through the alloy regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control over the metal-semiconductor alloy regions' positioning near the channel, reducing the need for epitaxial growth and lowering the thermal budget, thus enhancing contact quality and compatibility with 3D circuit production.
Implementation Method 1
amorphizing semiconductor regions of said surface semiconductor layer situated on either side of the gate block
Implementation Method 2
The semiconductor regions are advantageously amorphized by dopant implantation so as to concurrently dope the semiconductor regions of the surface semiconductor layer
Implementation Method 3
at least one activation annealing of dopants provided so as not to recrystallize, in particular not to render polycrystalline or monocrystalline, said amorphized semiconductor regions
Data Source
AI summary
Method for producing a metal-semiconductor alloy transistor source and drain comprising, in this order, the following steps:providing on a substrate (100) with an insulating layer (11) and a surface semiconductor layer (12) resting on the insulating layer (11): a transistor gate block (25) on this surface semiconductor layer (12) and insulating spacers (33) on either side of said gate block (25),amorphizing semiconductor regions (123) of said surface semiconductor layer (12) situated on either side of the gate block (25), whilst retaining at least one crystalline semiconductor zone (121) of the surface semiconductor layer (12) opposite the gate block (25),forming selectively with respect to said crystalline zone (121) of the surface semiconductor layer, metal-semiconductor alloy regions (125) in the amorphized semiconductor regions of the surface semiconductor layer (12).