Silicide Spiking Prevention in Shallow Source Drain Junctions
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Solution Overview
Problem
Existing shallow junction fabrication technologies, such as ion implantation followed by rapid thermal annealing, have not effectively addressed issues like junction punchthrough, current leakage, and elevated contact resistance in semiconductor devices as device dimensions continue to shrink, necessitating improved methods for forming shallow source/drain junctions.
Innovation Solution
A method involving the formation of a gate dielectric and gate on a semiconductor substrate, followed by the deposition of a metallic layer that reacts to form an early phase of silicide, with implanted shallow source/drain junctions formed beneath the silicide, and a final phase of silicide formed through high-temperature conversion, reducing junction leakage by preventing silicide spiking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ion implantation followed by rapid thermal annealing is used to form shallow junctions, then junction formation is achieved, but junction punchthrough and current leakage occur due to silicide spiking
Solution Approach 1:
The patent applies preliminary action by forming the shallow source/drain junctions through ion implantation before performing the siliciding process. This sequence ensures that the junctions are already in place at the desired depth before the silicide layer is formed, preventing the silicide from penetrating through and causing spiking. The preliminary junction formation establishes a barrier that stops the silicide reaction, thereby eliminating the harmful spiking effect while maintaining precise junction depth control.
2Area of moving object
If device dimensions are decreased to improve integration density, then packing density increases, but electrical resistance between contacts and substrate increases
Solution Approach 1:
The patent applies parameter changes by introducing a silicide layer with specific electrical properties that have lower resistance than the underlying silicon substrate. By forming cobalt silicide (CoSi2) or nickel silicide (NiSi2) at the contact interfaces, the electrical resistance is reduced despite the decreased device dimensions. This material parameter change compensates for the geometric scaling effects that would otherwise increase resistance.
3Ease of manufacture
If high-temperature annealing is performed to form final phase silicide, then silicide formation is complete, but junction leakage increases due to silicide penetration
Solution Approach 1:
The patent applies preliminary anti-action by performing the ion implantation to form shallow junctions before the high-temperature siliciding process. This preliminary action creates a dopant-rich region that acts as a barrier to silicide penetration. During the high-temperature annealing that forms the final phase silicide, the pre-formed junction prevents the silicide from penetrating through, thereby counteracting the potential harmful effect of high-temperature processing.
4Reliability
If transition material is deposited and annealed to form silicide, then contact resistance is reduced, but process complexity increases with multiple annealing steps
Solution Approach 1:
The patent applies merging by combining multiple process functions into unified steps. The ion implantation step simultaneously forms the shallow source/drain junctions and prepares the structure for subsequent siliciding. The high-temperature annealing step then performs dual functions: converting the transition material to final phase silicide while also activating the implanted dopants. This merging of functions reduces the total number of separate process steps compared to conventional approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly lowers junction leakage by ensuring the shallow source/drain junctions remain ahead of the silicide layers, maintaining continuous junctions and improving device performance by reducing current leakage and enhancing operating speeds.
Implementation Method 1
The semiconductor wafer is subjected to one or more annealing steps at temperatures above 700° C. and this causes the transition material to selectively react with the silicon and the polysilicon to form the metal silicide
Implementation Method 2
The silicon substrate on both sides of the polysilicon gate is slightly doped by ion implantation of boron or phosphorus impurity atoms into the surface of the silicon substrate
Implementation Method 3
Existing shallow junction fabrication technologies, such as ion implantation followed by rapid thermal annealing
Data Source
AI summary
An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.