Semiconductor Device Silicide Stress Management
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Solution Overview
Problem
Conventional semiconductor devices face reliability issues due to stress defects in the silicide layer, particularly near the boundary of N-type and P-type conductive impurity regions and the second semiconductor part, which can lead to threshold voltage variations and reduced device performance.
Innovation Solution
The semiconductor device incorporates a polycrystalline silicon layer with a first semiconductor part and a second semiconductor part of different widths, where the distance between these parts is 100 nm or more, and a silicide layer is formed on their surfaces, applying stress in opposite directions to reduce defects and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the silicide layer is formed on the upper surface of the first semiconductor part near the boundary of N-type and P-type conductive impurity regions, then the gate wiring function is achieved, but stress-induced defects occur in the silicide layer
Solution Approach 1:
The semiconductor layer is divided into a first semiconductor part and a second semiconductor part with different widths. The first semiconductor part has a first width and the second semiconductor part has a second width greater than the first width, creating a stepped structure that segments the stress distribution in the silicide layer.
Solution Approach 2:
The first semiconductor part is positioned at a distance of 100 nm or more from the boundary of the N-type and P-type conductive impurity regions. This local positioning strategy avoids the high-stress region near the PN junction boundary while maintaining the gate wiring function, thereby preventing stress-induced defects in the silicide layer.
2Area of stationary object
If the second semiconductor part with greater width is formed adjacent to the first semiconductor part, then the gate wiring coverage is improved, but additional stress is applied to the silicide layer near the second semiconductor part
Solution Approach 1:
The patent introduces a width dimension variation between the first and second semiconductor parts, creating a stepped structure in the planar view. This dimensional change allows the gate wiring to cover a larger area while distributing the stress across different regions, preventing concentration of stress near the second semiconductor part.
Solution Approach 2:
The first semiconductor part is pre-positioned at a distance of 100 nm or more from the PN junction boundary before forming the second semiconductor part. This preliminary positioning establishes a stress-free reference region that prevents subsequent stress propagation to the silicide layer.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, an insulating layer, a semiconductor layers and a silicide layer. The insulating layer is formed on the semiconductor substrate. The semiconductor layer is formed on the insulating layer and includes a polycrystalline silicon. The silicide layer is formed on the semiconductor layer. The semiconductor layer has a first semiconductor part and a second semiconductor part. The first semiconductor part includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type. The second semiconductor part is adjacent the second semiconductor region. In a width direction of the first semiconductor part, a second length of the second semiconductor part is greater than a first length of the first semiconductor part. A distance between the first and second semiconductor regions is 100 nm or more in an extension direction in which the first semiconductor region extends.