Silicide Stringer Removal via Extension Spacer Etch Back

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Solution Overview

Problem

In semiconductor fabrication, the formation of silicide 'stringers' due to concave notches in the liner oxide can lead to short circuits between device elements, as these notches promote unintended silicide formation during the silicide processing of MOS transistors.

Innovation Solution

The process involves etching back the extension spacer after silicide formation to expose and remove the silicide stringers, followed by additional processing such as argon sputtering to ensure complete removal and prevent further stringer formation, thereby modifying the conventional silicide processing sequence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the liner oxide is removed prior to silicide deposition, then the silicide formation process can proceed, but concave notches form in the exposed liner oxide which promote silicide stringer formation

Engineering Contradiction:
Improvesilicide formation processVSAvoidshort circuit prevention
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The extension spacer is etched back before silicide deposition to pre-eliminate the concave notches in the liner oxide. This preliminary action prevents the formation of silicide stringers before they can occur, allowing the silicide formation process to proceed without creating conductive paths between device elements.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If extension spacers are formed on sidewalls of gate electrode, then source/drain implant can be displaced from gate edges, but concave notches form in exposed liner oxide ends promoting silicide stringer formation

Engineering Contradiction:
Improvesource/drain placementVSAvoiddevice element isolation
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The extension spacer is etched back before silicide deposition to pre-eliminate the concave notches in the liner oxide. This preliminary action prevents the formation of silicide stringers before they can occur, allowing the silicide formation process to proceed without creating conductive paths between device elements.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If conventional silicide processing sequence is maintained, then processing simplicity is preserved, but silicide stringers form providing conductive paths between neighboring device elements

Engineering Contradiction:
Improveprocessing sequenceVSAvoidshort circuit prevention
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The extension spacer is etched back before silicide deposition to pre-eliminate the concave notches in the liner oxide. This preliminary action prevents the formation of silicide stringers before they can occur, allowing the silicide formation process to proceed without creating conductive paths between device elements.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents the formation of silicide stringers, enhancing the reliability of integrated circuits by eliminating conductive paths between neighboring device elements and improving dielectric gapfill capability in densely populated regions.

Implementation Method 1

The wafer is then heated in an inert ambient. Where the metal layer is in contact with silicon, the metal reacts with the silicon to form a silicide

Methodology Applied
Scientific EffectSilicide formation reaction: Chemical Bonding

Implementation Method 2

additional processing such as argon sputtering to ensure complete removal

Methodology Applied
Scientific EffectSputtering: Sputtering

Data Source

PatentUS7998822B2Semiconductor fabrication process including silicide stringer removal processing
Publication Date: 2011.08.16 VLSI TECHNOLOGY LLC
  • US7998822B2 patent drawing
  • US7998822B2 patent drawing
  • US7998822B2 patent drawing

AI summary

A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134). After the etch back the wafer (101) may be dipped in piranha solution and cleaned with an RF sputter (140) of argon.