Silicide Source/Drain Surrounding Gate Transistor for Low Resistance
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Solution Overview
Problem
High resistance in buried diffusion lines in integrated circuits leads to increased power consumption and reduced operation speed, and traditional field effect transistors have large cross-sectional areas limiting device density, necessitating the development of high-density, low-resistance interconnects and compact memory cell designs.
Innovation Solution
The implementation of vertically oriented field effect transistors with silicide elements as low-resistance conductors and contacts, where the first silicide element prevents carrier migration and the second silicide element provides low resistance contacts, allowing for a small cross-sectional area and efficient current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If dopant concentration is increased to reduce resistance of buried diffusion lines, then resistance decreases, but dopant diffusion into substrate increases making implantation harder to control
Solution Approach 1:
The patent changes the material parameter from doped semiconductor to silicide, fundamentally altering the electrical conductivity mechanism. Instead of relying on dopant concentration and diffusion control, the invention uses silicide formation which provides inherently lower resistance without the same diffusion control issues, directly resolving the contradiction between reducing resistance and maintaining implantation precision
Solution Approach 2:
The patent uses self-aligned silicide formation where the silicide precursor is deposited and then selectively removed, copying the pattern of exposed silicon regions. This self-aligned approach eliminates the need for precise dopant implantation control while achieving the desired low-resistance interconnects
2Loss of energy
If parallel metal lines are implemented to reduce loading effect, then resistance decreases, but device density decreases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar horizontal interconnect structures to vertical three-dimensional structures. The gate electrode extends vertically along the sidewalls of the channel region, and silicide elements are formed at different vertical levels, utilizing the vertical dimension to achieve both low resistance and high density without requiring parallel metal lines
Solution Approach 2:
The patent employs nested structures where the gate electrode surrounds the channel region vertically, and silicide elements are positioned within and around the channel structure at different levels. This nesting achieves complex interconnect functionality in a compact vertical arrangement, eliminating the need for separate parallel metal lines
3Ease of manufacture
If traditional horizontal field effect transistors are used, then manufacturing is simpler, but cross-sectional area is large limiting device density
Solution Approach 1:
The patent fundamentally changes the transistor architecture from horizontal planar structure to vertical three-dimensional structure. The channel region extends vertically, the gate electrode surrounds it vertically along sidewalls, and terminals are positioned at different vertical levels, achieving compact footprint while maintaining manufacturability through adapted fabrication processes
4Area of stationary object
If vertical field effect transistors are implemented to reduce cross-sectional area, then device density increases, but current drive capability may be insufficient
Solution Approach 1:
The patent uses composite material structures including silicide elements combined with doped semiconductor regions. The silicide provides low-resistance conductive paths while the doped semiconductor regions provide carrier injection and channel formation, achieving both compact size and sufficient current drive capability through material composition rather than increased area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces power consumption, enhances operation speed, and increases device density by minimizing the cross-sectional area of transistors while maintaining sufficient current drive.
Implementation Method 1
A self-aligned process for forming silicide involves depositing a silicide precursor over a substrate that includes exposed regions of silicon, and annealing the silicide precursor to form a silicide in the exposed regions
Data Source
AI summary
Field effect transistors described herein include first and second terminals vertically separated by a channel region. The first and second terminals comprise first and second silicide elements respectively. The first silicide element prevents the migration of carriers from the first terminal into the underlying semiconductor body or adjacent devices which can activate parasitic devices. The first silicide element is also capable of acting as a low resistance conductive line for interconnecting devices or elements. The second silicide element provides a low resistance contact between the second terminal and overlying elements.