Silicide Width Variation in Charge Trap Memory Gates
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Solution Overview
Problem
The existing techniques for nonvolatile semiconductor memory devices, particularly the charge trap type, face difficulties in configuring a structure similar to the floating gate type, as they lack an intergate insulating layer, making it challenging to control the threshold voltage and employ configurations that require fully silicided control gate electrodes.
Innovation Solution
A nonvolatile semiconductor memory device is designed with memory cell transistors and select transistors having gate electrodes with different silicide layers and materials, where the memory cell transistors have a first silicide layer of a specific width and the select transistors have a polysilicon layer and a larger silicide layer, allowing for different work functions and improved threshold voltage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the charge trap type structure is used without an intergate insulating layer, then the device can be manufactured with simpler structure, but it becomes difficult to control threshold voltage and employ fully silicided control gate electrodes
Solution Approach 1:
The gate electrode is segmented into two distinct parts: a control gate electrode for the memory cell transistor and a select gate electrode for the select transistor. This segmentation allows each gate to be independently configured with different silicide layer arrangements, enabling precise threshold voltage control for each transistor type while maintaining the overall simplicity of the charge trap type structure without requiring an intergate insulating layer
Solution Approach 2:
Different local structures are applied to different regions: the control gate electrode has a first silicide layer configuration optimized for memory cell threshold voltage control, while the select gate electrode has a second silicide layer configuration optimized for select transistor threshold voltage control. This local differentiation allows each region to have the specific properties needed for its function
2Manufacturing precision
If different gate electrode configurations are used for memory cell and select transistors, then threshold voltage control is improved, but device complexity increases
Solution Approach 1:
The control gate electrode and select gate electrode are merged into a single continuous gate electrode structure that extends across both the memory cell region and the select transistor region. This merging allows both gates to be formed in a single fabrication process step, reducing device complexity while still allowing different silicide layer configurations in different regions for precise threshold voltage control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the nonvolatile semiconductor memory device to set threshold voltages for memory cell and select transistors at suitable values, addressing the challenge of differing work functions and structural limitations in existing charge trap type devices.
Implementation Method 1
the first gate electrode is provided with a first silicide layer of a first width, the second gate electrode is provided with a silicide layer of a second width formed on the impurity-doped silicon layer, and the second width is larger than the first width
Data Source
AI summary
In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.