Silicide Work Function Tuning for Semiconductor Contact Resistance

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Solution Overview

Problem

As semiconductor devices continue to shrink, reducing contact resistance between silicide layers and underlying source/drain features becomes increasingly challenging, with existing methods not fully addressing the need for optimal work function matching and resistance reduction.

Innovation Solution

The method involves forming a P-type metal-containing silicide layer over P-type source/drain features and an N-type metal-containing silicide layer over N-type source/drain features, using a metal halide to selectively react with SiGe and Si, respectively, and a metal precursor to form interfacial layers with tuned work functions, thereby reducing Schottky barrier height and contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional silicide layers are used over source/drain features, then manufacturing is simpler, but contact resistance and Schottky barrier height remain high

Engineering Contradiction:
Improvecontact resistanceVSAvoidsilicide layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different metal compositions in different regions: a first metal composition is used in regions over P-type source/drain features, while a second metal composition is used in regions over N-type source/drain features. This local differentiation optimizes work function matching for each device type, reducing contact resistance and Schottky barrier height specifically where needed, rather than using a uniform silicide layer throughout.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs composite silicide layer structures combining different metal compositions. The silicide layer includes regions with first metal composition and regions with second metal composition, creating a composite material structure that simultaneously addresses the electrical requirements of both P-type and N-type devices, thereby reducing contact resistance without requiring entirely separate layer structures.

Inventive Principle:
Principle #40Composite materials

2Productivity

If device geometry is scaled down, then production efficiency increases and costs decrease, but contact resistance reduction becomes more challenging

Engineering Contradiction:
Improveproduction efficiencyVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the material parameter (metal composition) of the silicide layer to optimize work function matching. By selecting metals with appropriate work functions for P-type and N-type devices, the contact resistance is reduced at scaled dimensions. This parameter change allows the invention to maintain low contact resistance even as device geometry scales down and production efficiency increases.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces contact resistance and Schottky barrier height by matching work functions between silicide layers and source/drain features, improving device performance and efficiency.

Implementation Method 1

a metal halide to selectively react with SiGe and Si, respectively

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Implementation Method 2

a metal precursor to form interfacial layers with tuned work functions

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Data Source

PatentUS20240405023A1Semiconductor devices and methods of fabricating the same
Publication Date: 2024.12.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240405023A1 patent drawing
  • US20240405023A1 patent drawing
  • US20240405023A1 patent drawing

AI summary

A semiconductor device includes a semiconductor fin protruding from a substrate. The semiconductor device includes a P-type device over the semiconductor fin and an N-type device over the semiconductor fin. The P-type device includes a first source/drain (S/D) feature adjacent a first gate structure. The P-type device includes a dipole layer over the first S/D feature, where the dipole layer includes a first metal and a second metal different from the first metal. The P-type device further includes a first silicide layer over the dipole layer, where the first silicide layer includes the first metal. The N-type device includes a second S/D feature adjacent a second gate structure. The N-type device further includes a second silicide layer directly contacting the second S/D feature, where the second silicide layer includes the first metal, and where a composition of the second silicide layer is different from that of the dipole layer.