Silicided Bit Line Contacts With ONO Spacer Isolation
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Solution Overview
Problem
The formation of silicides in high-density memory devices with small features and close spacing between adjacent features leads to undesirable substrate leakage, which affects the operation of these devices.
Innovation Solution
The use of bit line oxide spacers to create an extended ONO foot, which prevents silicide contacts from shorting to the substrate, and the silicide formation is self-aligned to the ONO nitride edges, ensuring that silicide formation only occurs in the bit line contact region without extending between neighboring word-lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicides are formed on bit lines to reduce resistivity, then bit line contact resistance is reduced, but substrate leakage occurs due to close spacing between adjacent features
Solution Approach 1:
The patent segments the bit line structure by introducing separate oxide spacer regions between adjacent silicided bit line contacts. This segmentation physically divides the conductive path, preventing substrate leakage while maintaining low contact resistance in each individual contact region. The oxide spacers act as isolation barriers that segment the otherwise continuous bit line structure.
Solution Approach 2:
The patent introduces oxide spacers as intermediary elements between the silicided bit line contacts and the substrate. These oxide spacers serve as mediating structures that prevent direct electrical connection between adjacent contacts through the substrate, thereby eliminating substrate leakage while allowing each contact to maintain its low-resistance connection to the bit line.
2Productivity
If feature size is reduced and spacing is decreased to increase memory density, then storage density is improved, but silicide formation interferes with device operation due to substrate leakage
Solution Approach 1:
The patent applies segmentation by introducing oxide spacer regions that divide the densely packed bit line contacts into isolated segments. This allows high-density packaging of memory cells while preventing the substrate leakage that would otherwise occur when features are closely spaced. Each segmented contact region maintains its electrical integrity independently.
Solution Approach 2:
The patent applies local quality by creating regions with different electrical properties at different locations. The bit line contact regions have high conductivity (silicided), while the regions between contacts have high resistivity (oxide spacers). This local differentiation allows dense packing while preventing leakage paths through strategically placed high-resistivity regions.
3Object-affected harmful factors
If additional process steps are added to prevent substrate leakage, then substrate leakage is eliminated, but manufacturing complexity increases
Solution Approach 1:
The patent merges the oxide spacer formation with the existing ONO layer structure. The oxide spacers are formed as part of the ONO (oxide-nitride-oxide) layer deposition process, combining multiple functions into a single integrated structure. This eliminates the need for separate spacer formation steps while still providing the necessary isolation functionality.
Solution Approach 2:
The patent makes the ONO layer structure multi-functional by having it serve both as the charge trapping/dielectric structure and as the source of oxide spacers for isolation. The same oxide deposition process that creates the ONO layers also creates the oxide spacers when patterned appropriately, eliminating the need for dedicated spacer formation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents substrate leakage and reduces bit line contact resistance while maintaining high-density memory device performance by ensuring precise silicide formation without shorting, simplifying the semiconductor process and eliminating the need for additional steps like bit line contact implant and rapid thermal anneal.
Implementation Method 1
metal silicides can be formed on the surface of electrically conductive structures (e.g., bit lines) of the memory devices
Data Source
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AI summary
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges, A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.