Silicided Metal Gate CMP Stop Layer for Work Function Control
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Solution Overview
Problem
The shrinking feature sizes in CMOS devices pose challenges with polysilicon gate electrodes due to poly-depletion effects and gate sheet resistance, necessitating the transition to metal gate electrodes with tunable work functions for NMOS and PMOS devices.
Innovation Solution
The method involves forming a semiconductor device with silicided metal gates using a CMP stop layer and blocking layer, where a silicon nitride CMP stop layer is used to control the CMP process, allowing for differential removal rates to expose the gate electrodes while protecting the source/drain regions, and subsequent silicidation to achieve the desired work function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon gate electrodes are used in traditional CMOS devices, then the manufacturing process is simpler, but poly-depletion effects and gate sheet resistance become serious issues as device feature sizes shrink
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal (such as tungsten, cobalt, or nickel), fundamentally altering the electrical properties to eliminate poly-depletion effects and reduce gate sheet resistance. This material substitution enables the gate to achieve the required work functions (4.1-4.4 eV for NMOS, 4.8-5.1 eV for PMOS) while maintaining compatibility with existing CMOS fabrication processes.
Solution Approach 2:
The patent employs a composite gate structure consisting of a metal gate electrode combined with a silicide layer formed through self-aligned silicidation. This composite structure provides both the low resistance benefits of metal and the tunable work function characteristics needed for optimized threshold voltage control in high-performance devices.
2Reliability
If metal gate electrodes are used to achieve tunable work functions, then threshold voltage optimization is improved, but the manufacturing process complexity increases due to the need for precise work function control
Solution Approach 1:
The patent controls the work function of metal gates by selecting specific metal materials and adjusting their thickness parameters. By choosing metals with appropriate intrinsic work functions and controlling deposition thickness, the gate achieves the required work function range (4.1-4.4 eV for NMOS, 4.8-5.1 eV for PMOS) without requiring complex post-processing adjustments.
Solution Approach 2:
The patent introduces a silicide layer as an intermediary between the metal gate electrode and the channel region. This silicide layer serves as a mediator that modifies the effective work function of the gate while providing a self-aligned formation process that simplifies manufacturing by eliminating the need for precise metal thickness control to achieve the desired work function.
3Manufacturing precision
If a CMP process is used to remove bulk oxide layer, then planarization is improved, but the CMP stop layer must be precisely controlled to prevent damage to gate electrodes
Solution Approach 1:
The patent introduces a CMP stop layer (such as silicon nitride or silicon oxynitride) as an intermediary protective layer between the bulk oxide and the gate electrode. This stop layer has selective etch resistance that allows the CMP process to effectively remove the bulk oxide for planarization while automatically stopping before damaging the underlying gate electrode, providing built-in process control.
Solution Approach 2:
The CMP stop layer exhibits different removal rates under CMP conditions compared to the bulk oxide layer. This local quality difference in etch resistance allows the CMP process to selectively remove the bulk oxide while preserving the stop layer, creating a self-limiting process that prevents gate electrode damage without requiring complex process monitoring.
4Reliability
If silicided metal gates are formed by consuming polysilicon, then contamination issues are avoided and process compatibility is improved, but the polysilicon layer must be completely consumed which adds process steps
Solution Approach 1:
The patent performs preliminary deposition of a metal layer over the polysilicon gate electrode before the silicidation reaction. This preliminary action ensures that the metal is in place to react with the polysilicon, and the subsequent self-aligned silicidation process automatically consumes the polysilicon to form the silicided metal gate, eliminating contamination risks from deposited metal gates while maintaining process efficiency.
Solution Approach 2:
The silicidation process is self-aligned and self-limiting, where the metal layer automatically reacts with the polysilicon gate electrode to form the silicided structure. The reaction consumes the polysilicon completely and stops when the metal is depleted, providing automatic process control that eliminates the need for additional process steps to manage polysilicon consumption while ensuring contamination-free gate formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control over the CMP process, minimizes gate electrode damage, and achieves the required work function for metal gates, addressing the issues of poly-depletion and gate sheet resistance in CMOS devices.
Implementation Method 1
The bulk oxide layer is removed with a CMP process to expose at least the CMP stop layer located over the gate electrode, wherein a removal rate of the bulk oxide layer is at least about 3 times greater than a removal rate of the CMP stop layer
Implementation Method 2
the bulk oxide and the CMP stop layer located over the source/drains are removed with a wet etch, wherein a wet etch removal rate of the CMP stop layer is at least about 10 times greater than a removal rate of the blocking layer
Implementation Method 3
the silicided metal gate provides a metal gate with the least perturbation to the conventional process and avoids contamination issues
Data Source
AI summary
In one aspect, there is provided a method of manufacturing a semiconductor device that comprises placing a blocking layer, a CMP stop layer and a bulk oxide layer over an oxide cap layer that is located over gate structures and source/drains located adjacent thereto. The bulk oxide layer and the CMP stop layer are removed with a CMP process to expose the top of gate electrodes and are removed from over the source/drain areas with a wet etch. The CMP stop layer has a CMP removal rate that is less than a CMP removal rate of the bulk oxide layer and has a wet etch removal rate that is greater than a wet etch removal rate of the blocking layer.