Silicided Vertical Power MOSFET Gates for Faster Signal Propagation
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Solution Overview
Problem
High resistivity of p-doped polysilicon gates in power MOSFETs leads to increased gate resistance and slow signal propagation, especially in lower voltage high performance circuits, and the integration of CMOS devices with power transistors on the same silicon die is hindered by pn diodes in complementary doped polysilicon lines.
Innovation Solution
Incorporating a metal silicide region in the upper central part of doped polycrystalline silicon gate electrodes of both NMOS and PMOS cells reduces gate resistance and improves signal propagation, enabling low and matched threshold devices with a single gate oxide thickness, facilitating the monolithic integration of CMOS devices with power transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If p-doped polysilicon gates are used for PMOS cells, then the device can be integrated with power transistors on the same silicon die, but the gate resistance increases and signal propagation slows down
Solution Approach 1:
The patent applies composite materials by combining p-doped polysilicon with metal silicide (such as cobalt silicide or nickel silicide) to form a composite gate electrode structure. This composite structure leverages the low resistivity of metal silicide to reduce gate resistance while preserving the p-doped polysilicon's compatibility with PMOS devices and power transistors, thereby achieving both integration capability and high-speed performance
Solution Approach 2:
The patent applies local quality by selectively forming metal silicide regions only in specific areas of the gate electrode, particularly at the upper central part where current density is highest. This localized modification reduces gate resistance where it matters most for signal propagation, while maintaining the p-doped polysilicon structure in other regions to ensure proper device operation and integration
2Adaptability or versatility
If p-doped polysilicon gates are used for PMOS cells, then CMOS integration is enabled, but the gate resistance becomes rather high
Solution Approach 1:
The patent uses composite materials by creating a hybrid gate electrode consisting of p-doped polysilicon and metal silicide layers. The metal silicide component provides low resistivity to improve gate reliability and reduce RC time constants, while the p-doped polysilicon maintains the necessary electrical characteristics for PMOS operation and enables CMOS integration with NMOS devices
Solution Approach 2:
The patent applies parameter changes by modifying the gate electrode's electrical parameters through the addition of metal silicide. This changes the overall resistivity of the gate structure from high (pure p-doped polysilicon) to low (composite with metal silicide), thereby improving gate reliability and signal drive capability while maintaining CMOS compatibility
3Power
If gate dimensions are shrunk for lower voltage high performance circuits, then circuit performance improves, but gate resistance increases due to p-doped polysilicon
Solution Approach 1:
The patent applies composite materials to address the scaling challenge by combining p-doped polysilicon with metal silicide in the gate electrode. As gate dimensions shrink for lower voltage high-performance circuits, the metal silicide component becomes increasingly important to maintain low gate resistance, enabling continued scaling without sacrificing drive capability or signal propagation speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of metal silicide regions in polysilicon gates lowers gate resistance and enhances signal propagation, supporting high performance, high frequency DCDC power supplies and enabling efficient integration of CMOS devices with power transistors on the same semiconductor die.
Implementation Method 1
an upper central part of each of the gate electrodes of the power transistor cells is occupied by a metal silicide region that adjoins the doped polycrystalline silicon
Data Source
AI summary
A semiconductor device includes a vertical power transistor having a plurality of power transistor cells. Each power transistor cell includes a source region at a first main surface of a semiconductor substrate, a drain region at a second main surface of the semiconductor substrate opposite the first main surface, a gate trench extending into the semiconductor substrate from the first main surface, a gate electrode in the gate trench and comprising doped polycrystalline silicon, and a dielectric material separating the gate electrode from the semiconductor substrate. An upper central part of each of the gate electrodes of the power transistor cells is occupied by a metal silicide region that adjoins the doped polycrystalline silicon. A method of producing the semiconductor device is also described.