Silicided Source/Drain Epitaxial Transistor for Mobility and Resistance
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to reduce short channel effects and improve charge carrier mobility in scaled-down MOS transistors, particularly in PMOS transistors, while minimizing contact resistance and sheet resistance.
Innovation Solution
The solution involves forming a semiconductor device with a silicided source/drain region using epitaxial layers, specifically SiGe for PMOS transistors and Si for NMOS transistors, where the epitaxial layers are grown using selective epitaxial growth processes to apply compressive stress and improve mobility, and silicide layers are formed to reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOS transistors are scaled down to increase integration density, then device integration is improved, but short channel effects worsen and degrade operational characteristics
Solution Approach 1:
The patent applies selective stress to specific regions of the transistor channel through silicided source/drain structures. By locally modifying the source and drain regions with silicide layers, the channel receives targeted stress that improves carrier mobility without requiring overall device scaling changes, thus maintaining operational characteristics while enabling higher integration.
Solution Approach 2:
The patent changes the physical and chemical parameters of the source/drain regions by forming silicide compounds (such as nickel silicide, cobalt silicide) with specific stoichiometries and crystal structures. This parameter change in the source/drain material composition creates stress in the channel that improves carrier mobility, allowing scaled devices to maintain performance.
2Reliability
If silicide layers are formed to reduce contact resistance and sheet resistance, then electrical performance is improved, but fabrication complexity increases
Solution Approach 1:
The patent performs silicide formation at an early stage in the fabrication process, before final contact formation. By preliminarily forming the silicide layers on source/drain regions early in the process flow, subsequent contact holes can be formed directly through the silicide to reach the substrate, eliminating the need for separate contact resistance reduction steps and simplifying overall fabrication.
Solution Approach 2:
The silicide layers serve multiple functions simultaneously: they reduce contact resistance at metal contacts, reduce sheet resistance in the source/drain regions, and provide stress to the channel for improved mobility. This multi-functionality consolidates several process steps into one, reducing overall fabrication complexity despite the added silicide formation step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the operational characteristics of both PMOS and NMOS transistors by increasing charge carrier mobility and reducing contact resistance, thereby improving the overall performance and integration density of semiconductor devices.
Implementation Method 1
the epitaxial layers are grown using selective epitaxial growth processes to apply compressive stress and improve mobility
Implementation Method 2
silicide layers are formed to reduce resistance
Data Source
AI summary
A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.