Silicided Nonvolatile Memory Split Gate RC Delay Reduction
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Solution Overview
Problem
Nonvolatile memory devices with split gate bitcells require efficient silicidation of both control and select gates to reduce RC delay, especially for gates not connected to metal lines over long distances, to achieve faster read access times.
Innovation Solution
A method for forming nonvolatile memory devices where both control and select gates are silicided, with specific processes involving polysilicon layers, nitride layers, and annealing to form silicide regions, ensuring electrical isolation and minimizing RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If control gates and select gates are silicided to reduce RC delay, then read access time is improved, but device complexity increases due to additional processing steps
Solution Approach 1:
The patent combines the silicidation of control gates and select gates into a single integrated process flow. By using a common polysilicon deposition and annealing sequence for both gate types, the methodology merges what would otherwise be separate processing steps, reducing overall complexity while achieving RC delay reduction for both gates simultaneously.
Solution Approach 2:
The patent performs preliminary patterning and isolation structure formation before silicidation. By pre-defining the gate regions and installing isolation structures (such as nitride or oxide spacers) beforehand, the subsequent silicidation process can proceed uniformly across both control and select gates without requiring additional masking or protection steps, thereby simplifying the overall process.
2Reliability
If select gate is recessed relative to control gate, then silicide separation is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces intermediary isolation structures (nitride or oxide spacers) between the control gate and select gate silicides. These spacers act as mediators that physically separate the silicide regions and prevent electrical interaction. The spacers are deposited conformally and then etched back, creating a controlled separation that relaxes alignment precision requirements compared to direct recessed structures.
Solution Approach 2:
The patent segments the gate structure into distinct control gate and select gate regions with physical separation. By dividing the continuous gate structure into separated segments using isolation spacers, the patent achieves independent silicide formation on each gate type, ensuring reliable electrical isolation while maintaining manufacturability through standard spacer deposition and etch processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The silicidation of both control and select gates in nonvolatile memory devices reduces RC delay, enhancing read access times and programming efficiency, particularly for devices with long gate distances.
Implementation Method 1
One way to reduce this RC delay is by silicidation of not only the select gate portion of the memory device but by silicidation of the control gate portions of the memory device as well
Implementation Method 2
A process for forming a nonvolatile memory device with silicided control and select gates
Data Source
AI summary
A memory device is formed on a semiconductor substrate. A select gate electrode and a control gate electrode are formed adjacent to one another. One of either the select gate electrode or the control gate electrodes is recessed with respect to the other. The recess allows for a manufacturable process with which to form silicided surfaces on both the select gate electrode and the control gate electrode.