Silicided Strain Control Layers in Semiconductor Devices
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Solution Overview
Problem
As semiconductor devices miniaturize, strain relaxation in strained semiconductor layers becomes significant, leading to increased resistance in source/drain regions and degradation of device characteristics, necessitating effective strain control techniques to maintain performance.
Innovation Solution
The implementation of silicided strain control layers, formed by combining strained semiconductor layers with different lattice constants and undergoing silicidation, allows for controlled strain application and reduced resistance in source/drain regions, thereby maintaining strain and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the device size is miniaturized to improve integration degree, then the active layer size is reduced, but strain relaxation occurs leading to increased resistance and degraded device characteristics
Solution Approach 1:
The patent applies different materials with different lattice constants to different regions: SiGe layers are placed specifically in the source/drain regions while the channel region maintains its strained Si structure. This local differentiation allows strain relaxation to be confined to non-critical regions while preserving carrier mobility in the channel.
Solution Approach 2:
The SiGe layers are formed on the strained Si layer before the final device fabrication steps. This preliminary action of introducing strain control layers early in the process prevents strain relaxation from occurring during subsequent processing and miniaturization.
2Reliability
If strain control layers are formed to prevent strain relaxation, then device characteristics are maintained, but the source/drain regions become smaller requiring increased layer thickness which generates high resistance
Solution Approach 1:
The patent changes the material parameter (lattice constant) by using SiGe layers with varying Ge concentrations. By adjusting the Ge content, the lattice constant is optimized to provide sufficient strain control while maintaining low resistance in the source/drain regions.
Solution Approach 2:
The patent uses composite material structures combining Si and Ge in specific ratios to create SiGe layers. This composite approach allows simultaneous achievement of strain control (through lattice mismatch) and low resistance (through optimized composition and thickness).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a high-performance semiconductor device with lower resistance in source/drain regions and improved mobility, while preventing strain relaxation and maintaining device characteristics, even in miniaturized devices.
Implementation Method 1
a mixed crystal layer made of a material having a larger lattice constant than that of Si, or a strain-relaxed SiGe mixed crystal layer (hereinafter referred to simply as the SiGe layer) having a Ge concentration of 20%, for example, is formed on a Si substrate, and a Si layer is formed on the SiGe layer. The strain derived from the difference in lattice constant is applied to the Si layer, and the Si layer turned into a strained Si layer.
Implementation Method 2
The implementation of silicided strain control layers, formed by combining strained semiconductor layers with different lattice constants and undergoing silicidation, allows for controlled strain application and reduced resistance in source/drain regions
Data Source
AI summary
A semiconductor device according to an embodiment includes: a substrate; a first semiconductor layer formed on the substrate and having a strain; a second and a third semiconductor layers formed at a distance from each other on the first semiconductor layer, and having a different lattice constant from a lattice constant of the first semiconductor layer; a gate insulating film formed on a first portion of the first semiconductor layer, the first portion being located between the second semiconductor layer and the third semiconductor layer; and a gate electrode formed on the gate insulating film. At least one of outer surface regions of the second semiconductor layer and a second portion of the first semiconductor layer is a first silicide region, and at least one of outer surface regions of the third semiconductor layer and a third portion of the first semiconductor layer is a second silicide region, the second and third portions being located immediately below the second and third semiconductor layers respectively.