Siliciding Method for Integrated Circuit Regions
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Solution Overview
Problem
Conventional siliciding methods in integrated circuit manufacturing result in high resistivity and potential degradation of transistor performance due to uniform silicide formation, lacking the ability to tailor silicide thickness and resistance in different regions.
Innovation Solution
A method involving selective siliciding of semiconductor regions with varying metal layer thicknesses and annealing temperatures to form thick, low-resistance silicide in high-voltage regions and thin, stable silicide in low-voltage regions, using nickel metal layers and carbon or germanium implantation to control silicide formation and reduce Schottky barriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional siliciding method is used to form silicide in all regions, then resistivity is decreased in silicided regions, but Schottky barrier remains high and transistor performance degrades
Solution Approach 1:
The patent applies local quality by differentiating silicide formation between high-voltage and low-voltage regions. Low-voltage regions receive no silicide or thin silicide to maintain low Schottky barrier and preserve transistor performance, while high-voltage regions receive thick silicide to achieve low resistivity. This spatial differentiation of silicide thickness resolves the contradiction between reducing Schottky barrier and decreasing resistivity.
2Adaptability or versatility
If uniform silicide thickness is formed across all regions, then manufacturing process is simple, but cannot optimize both low-resistance and low-Schottky-barrier requirements simultaneously
Solution Approach 1:
The patent segments the siliciding process into distinct stages: first siliciding for high-voltage regions, selective removal or masking, and second siliciding for low-voltage regions. This segmentation enables different silicide thicknesses to be formed in different regions, achieving region-specific optimization while managing process complexity through systematic division of steps.
Solution Approach 2:
The patent employs preliminary action by performing first siliciding on high-voltage regions before addressing low-voltage regions. The initial silicide layer is formed, then selectively removed or masked in low-voltage areas, followed by controlled second siliciding. This preliminary formation and selective modification approach enables precise control over final silicide distribution.
3Reliability
If thick silicide is formed in all regions to decrease resistivity, then electrical contact resistance is reduced, but transistor performance degrades due to excessive Schottky barrier
Solution Approach 1:
The patent applies local quality by forming thick silicide exclusively in high-voltage regions where low contact resistance is critical, while maintaining thin or no silicide in low-voltage transistor contact regions where low Schottky barrier is essential for performance. This spatial differentiation resolves the contradiction between needing low resistivity and avoiding excessive Schottky barrier.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves reduced Schottky barriers and improved transistor performance by forming thick, low-resistance silicide in high-voltage regions and thin, stable silicide in low-voltage regions, optimizing resistivity and stability without degrading transistor performance.
Implementation Method 1
a step of siliciding regions comprising silicon, which are intended to form electric contact areas, is generally provided, in order to decrease their resistivity
Implementation Method 2
the atoms are carbon and/or germanium atoms
Data Source
AI summary
An integrated circuit includes first semiconductor regions each having a silicided portion with group-III, group-IV, and/or group-V atoms implanted therein. In each first semiconductor region, a concentration of the group-III, group-IV, and/or group-V atoms is maximum at an interface between the silicided portion and a non-silicided portion. Other semiconductor regions in the integrated circuit each include a silicided portion also having group-III, group-IV, and/or group-V atoms implanted therein. The silicided portions of the first semiconductor regions are thicker than the silicided portions of the other semiconductor regions. The group-III, group-IV, and/or group-V atoms of the first semiconductor regions and of the other semiconductor regions may be carbon and/or germanium atoms.