Semiconductor Bit Line Air Gaps for Lower RC Delay
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Solution Overview
Problem
The increasing parasitic capacitance due to reduced spacing between conductive devices in semiconductor structures leads to RC delay, affecting the working efficiency of semiconductor devices.
Innovation Solution
Formation of air gaps between the conductive lines (BLs) in the semiconductor structure, exposing parts of their side surfaces, which reduces the dielectric constant and thereby decreases parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacing between adjacent conductive devices (bit lines) is decreased to achieve higher integration level, then the integration density is improved, but the parasitic capacitance increases causing RC delay and affecting working efficiency
Solution Approach 1:
The patent changes the dielectric parameter by replacing conventional insulating materials with air gaps (dielectric constant ≈1) in the regions between bit lines. This parameter change reduces the parasitic capacitance between adjacent conductive devices while maintaining the reduced spacing for high integration density.
Solution Approach 2:
The patent introduces air gaps as an intermediary substance between adjacent bit lines. These air gaps act as a mediator that reduces the electric field coupling between conductive devices, thereby reducing parasitic capacitance while allowing the bit lines to remain closely spaced for high integration.
2Productivity
If the spacing between bit lines is decreased to improve integration, then device density is improved, but RC delay increases due to increased parasitic capacitance
Solution Approach 1:
The patent modifies the dielectric constant parameter in the region between bit lines by introducing air gaps. This parameter change directly reduces parasitic capacitance, thereby reducing RC delay and allowing faster signal propagation despite the reduced spacing between bit lines for high device density.
3Ease of manufacture
If conventional insulating material is used between conductive devices, then manufacturing is simplified, but parasitic capacitance is high reducing working efficiency
Solution Approach 1:
The patent extracts the insulating material from the region between bit lines and replaces it with air gaps. This removal of conventional insulating material eliminates the source of high parasitic capacitance while the air gaps provide the necessary electrical isolation with minimal dielectric constant.
Solution Approach 2:
The patent uses air (inert atmosphere) as the dielectric medium between bit lines instead of conventional insulating materials. The air gaps provide electrical isolation with a dielectric constant of approximately 1, minimizing parasitic capacitance while maintaining manufacturing feasibility through standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces parasitic capacitance and enhances the working efficiency of the semiconductor structure by utilizing the low dielectric constant of air in the gaps between BLs.
Implementation Method 1
As the air has a dielectric constant of about 1, the dielectric constant of the structure between the BLs is reduced, thus reducing the parasitic capacitance
Data Source
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AI summary
The present disclosure provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and solves the technical problem of a high parasitic capacitance of the semiconductor structure. The manufacturing method of the semiconductor structure includes: providing a substrate, a plurality of spaced first trenches being formed in the substrate; forming a sacrificial layer in the first trenches and a first protective layer on the sacrificial layer, the sacrificial layer and the first protective layer filling up the first trenches, and the first protective layer in the first trenches being provided with etching holes penetrating through the first protective layer; removing the sacrificial layer with the etching holes to form air gaps; and carrying out a silicification reaction on the substrate between adjacent ones of the first trenches and close to bottoms of the first trenches to form bit lines (BLs) in the substrate, parts of side surfaces of the BLs being exposed in the air gaps. By forming the air gaps, and exposing parts of the side surfaces of the BLs in the air gaps, the present disclosure reduces the dielectric constant of the structure between the BLs and the parasitic capacitance of the semiconductor structure.