III-V on Silicon Bonding Trenches for Moisture Venting
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Solution Overview
Problem
Hybrid semiconductor optical devices face issues with bonding defects due to water vaporization at the interface, leading to bubble formation and potential etching of the semiconductor device during wet-etching, which can cause performance degradation.
Innovation Solution
The semiconductor optical device incorporates a substrate with trenches that extend from the semiconductor device region to outside, featuring a single communicating port for moisture discharge, preventing etchant ingress and maintaining device integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If hydrophilic bonding is performed to bond the semiconductor device to the silicon layer, then bonding strength is improved, but water is generated and vaporized at the bonding interface causing bubble formation and bonding defects
Solution Approach 1:
The patent extracts the harmful water by providing trenches in the silicon layer that extend from the bonding interface to the surface, allowing water to be discharged outside the bonding interface rather than accumulating there. This prevents bubble formation while maintaining the hydrophilic bonding process.
Solution Approach 2:
The trenches act as an intermediary structure between the bonding interface and the external environment, providing a dedicated pathway for water removal. The trenches mediate the conflict between maintaining bonding strength and preventing water accumulation by offering a separate channel for water evacuation.
2Reliability
If trenches are provided in the silicon layer for water drainage, then bubble formation is reduced, but multiple communicating ports may allow etchant ingress during wet-etching causing semiconductor device etching
Solution Approach 1:
The patent creates an asymmetric trench structure with only one communicating port per trench, breaking the symmetry that would otherwise provide multiple entry points for etchant. This asymmetric design maintains water drainage capability while minimizing etchant ingress risk.
Solution Approach 2:
The patent segments the water drainage function into multiple trenches, each with a single communicating port. This segmentation distributes the water removal function across multiple controlled access points, reducing the probability of etchant entering compared to a single large opening.
3Productivity
If multiple communicating ports are provided in trenches for effective water drainage, then moisture removal is improved, but the number of entry points for etchant increases during wet-etching
Solution Approach 1:
The patent segments the water drainage system into multiple separate trenches, each with a single communicating port. This segmentation achieves effective water drainage through distributed pathways while minimizing the total number of exposed entry points compared to having multiple ports in fewer trenches.
Solution Approach 2:
The patent applies different local qualities to different parts of the trench system: the trenches have open communicating ports for water access, but the trench structures themselves provide localized protection and control over etchant exposure. Each trench's single port location and orientation are optimized for water removal while minimizing etchant access.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents etching of the semiconductor device from the bonding interface, reducing defects and enhancing performance by ensuring moisture is discharged through the trenches, thereby maintaining device stability and functionality.
Implementation Method 1
When the water is vaporized at the bonding interface, bubbles are generated
Data Source
AI summary
A semiconductor optical device includes a substrate including a silicon layer, and a semiconductor device formed of a III-V group compound semiconductor and bonded to the silicon layer of the substrate. The silicon layer is provided with at least one trench, the at least one trench extends from a region overlapping the semiconductor device to a region outside the semiconductor device and is provided with a communicating port that communicates between a portion of the at least one trench in the region overlapping the semiconductor device and a portion of the at least one trench in the region outside the semiconductor device, and the communicating port in the at least one trench is a single communicating port.


