Silicon Boron Nitride Charge Trapping Layer for Non-Volatile Memory Erase Speed

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Solution Overview

Problem

Non-volatile memory devices with charge trapping layers face limitations in erase speed due to low trap density and high voltage requirements, leading to backward tunneling errors and increased threshold voltage.

Innovation Solution

A non-volatile memory device structure incorporating a charge trapping layer with a nitride layer and a silicon boron nitride layer, or a triple-layer structure with additional nitride layers, to enhance trap density and prevent backward tunneling, along with a blocking layer and control gate electrode configuration to improve erase characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a conventional charge trapping layer with low trap density is used, then device structure is simple, but erase speed is slow and high voltage is required causing backward tunneling

Engineering Contradiction:

Improveerase speedVSAvoidcharge trapping layer structure

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The charge trapping layer is divided into multiple sub-layers with different materials (first nitride layer, silicon boron nitride layer, second nitride layer) and different trap densities. This segmentation allows each layer to contribute differently to charge trapping, increasing overall trap density and erase speed while managing the complexity through a systematic multi-layer approach

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent uses composite material structure combining different nitride-based materials (silicon nitride and silicon boron nitride) in the charge trapping layer. The silicon boron nitride layer provides high trap density while the silicon nitride layers provide structural stability and interface quality, creating a composite structure that achieves both high erase speed and reliable device operation

Inventive Principle:

Principle #40Composite materials

2Speed

If high voltage is applied to increase erase speed, then erase speed improves, but backward tunneling occurs causing programming errors

Engineering Contradiction:

Improveerase speedVSAvoidprogramming accuracy

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent changes the material composition parameters of the charge trapping layer by introducing silicon boron nitride with high trap density. This parameter change allows the device to achieve high erase speed at lower voltages because the increased trap density enhances the efficiency of charge trapping and release processes, eliminating the need for high voltage that would cause backward tunneling

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The blocking layer serves as an intermediary between the charge trapping layer and the control gate electrode. It prevents electrons from the control gate from tunneling backward into the charge trapping layer during erase operations, thereby preventing programming errors while allowing efficient erase at reduced voltages

Inventive Principle:

Principle #24Intermediary (Mediator)

3Quantity of substance

If conventional nitride layer is used, then manufacturing process is simple, but trap density is low limiting erase performance

Engineering Contradiction:

Improvetrap densityVSAvoidcharge trapping layer structure

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The charge trapping layer is segmented into multiple sub-layers with different materials (first nitride layer, silicon boron nitride layer, second nitride layer) and different trap densities. This segmentation allows each layer to contribute differently to charge trapping, increasing overall trap density and erase speed while managing the complexity through a systematic multi-layer approach

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed structure increases erase speed and maintains retention characteristics without deteriorating the memory device's stability, reducing the need for high erase voltages and minimizing programming errors.

Implementation Method 1

a tunneling layer, a charge trapping layer including a nitride layer and a silicon boron nitride layer over the tunneling layer

Methodology Applied

Scientific EffectQuantum tunneling:

Implementation Method 2

hot electrons are trapped from the substrate 100 into a trap site of the silicon nitride layer 120 as a charge trapping layer

Methodology Applied

Scientific EffectCharge trapping:

Data Source

PatentUS8294200B2Non-volatile memory device

Publication Date: 2012.10.23 SK HYNIX INC

AI summary

A non-volatile memory device includes a substrate, a tunneling layer over the substrate, a charge trapping layer including a nitride layer and a silicon boron nitride layer over the tunneling layer, and a blocking layer over the charge trapping layer, and a control gate electrode arranged on the blocking layer.