Silicon Bridge Interconnect for High-Density Chip Stacking
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Solution Overview
Problem
The challenge in packaging integrated circuits (ICs) is to achieve high-density die-to-die connections while maintaining robustness and controlling costs, as reduced spacing requirements lead to increased costs and potential fragility.
Innovation Solution
The use of small dimension silicon interposers, such as silicon bridges, in conjunction with laminate spacers and conductive interposers, facilitates high-density chip-to-chip interconnection, enabling robust and cost-effective 2.5D packaging solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If spacing between IC packages is reduced to achieve high-density wiring, then wiring density is improved, but robustness deteriorates and manufacturing cost increases
Solution Approach 1:
The patent introduces an intermediary substrate that acts as a mediator between multiple IC packages. This substrate provides a platform for high-density interconnection without requiring the IC packages themselves to be in direct close contact, thereby maintaining their robustness while achieving high wiring density through the intermediary structure.
Solution Approach 2:
The patent transitions from planar two-dimensional packaging to three-dimensional vertical stacking architecture. By utilizing the vertical dimension with multiple layers of substrates and IC packages stacked together, the system achieves high wiring density without reducing horizontal spacing, thus maintaining robustness while increasing interconnection capacity.
2Productivity
If spacing between IC packages is reduced to achieve high-density wiring, then wiring density is improved, but manufacturing cost increases
Solution Approach 1:
The patent employs preliminary action by pre-assembling substrate-IC packages stacks and preparing interconnection structures before final integration. This allows for standardized manufacturing processes and modular assembly, reducing overall manufacturing complexity and cost while enabling high wiring density through planned vertical stacking arrangements.
3Quantity of substance
If multiple die are integrated in CPU and components to approach Moore's law limit, then transistor density is improved, but interconnection complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the integrated system into multiple discrete IC packages, each containing optimized transistor arrays. These segmented packages are then interconnected through vertical stacking on substrates, which simplifies the interconnection architecture compared to integrating all transistors and interconnections in a single monolithic structure.
Solution Approach 2:
The patent resolves interconnection complexity by transitioning from two-dimensional planar interconnection to three-dimensional vertical interconnection. Multiple IC packages are stacked vertically with interconnection layers between substrates, enabling high transistor density across multiple die while managing interconnection complexity through vertical routing rather than dense horizontal wiring.
Data Source
AI summary
A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.