Silicon Bridge Die Stacking Without Solder for Dense Packaging
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to enhance integration density and reduce package size while improving processing rates and minimizing heat consumption, particularly in multi-chip structures where efficient electrical communication between dies is required without the use of solder connections.
Innovation Solution
A semiconductor structure is designed with a silicon bridge interconnection die that provides solder-less electrical communication between dies, utilizing redistribution layers and through vias to facilitate signal transmission, and is encapsulated with insulating materials for a flat, planar surface, allowing for efficient packaging and reduced heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If solder connections are used between dies, then electrical communication between dies is achieved, but heat consumption increases and processing rate decreases
Solution Approach 1:
The patent extracts and eliminates the solder material from the interconnection process. By removing the solder layer entirely and replacing it with direct die-to-die bonding through bumped contacts, the harmful thermal effects of solder are eliminated, reducing heat consumption while improving processing efficiency.
Solution Approach 2:
The patent introduces an intermediary bumped contact structure that facilitates direct electrical and mechanical connection between dies without requiring solder. The bumps serve as intermediate elements that enable reliable electrical communication while avoiding the thermal drawbacks of solder joints.
2Quantity of substance
If integration density is increased, then more components are integrated into a given area, but package size reduction becomes more challenging
Solution Approach 1:
The patent transitions from two-dimensional planar packaging to three-dimensional stacked packaging. By stacking dies vertically and connecting them through bumped contacts, the system achieves higher integration density without proportionally increasing the package footprint, effectively utilizing the vertical dimension to accommodate more components.
Solution Approach 2:
The patent implements a nested structure where multiple dies are stacked one on top of another, with each die containing functional components and interconnection structures. This nested arrangement allows multiple functional layers to be integrated within a compact package volume, increasing integration density while controlling package size.
3Quantity of substance
If minimum feature size is reduced, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the interconnection function into discrete bumped contacts rather than continuous conductive paths. This segmentation allows for more tolerant alignment and reduces the precision requirements for feature size control, as the bumped contacts can accommodate certain variations in positioning while maintaining reliable electrical connection.
Data Source
AI summary
A semiconductor structure includes a first die, a first bonding structure, a first encapsulant, a second die, a second bonding structure and a second encapsulant. The first bonding structure includes a first dielectric layer and a first conductive pad in the first dielectric layer. The first encapsulant laterally encapsulates the first die and the first dielectric layer. The second bonding structure includes a second dielectric layer and second conductive pads in the second dielectric layer. The second encapsulant laterally encapsulates the second die and the second dielectric layer. The first conductive pad is physically connected to one of the second conductive pads, opposite sidewalls of the first dielectric layer is within opposite sidewalls of the first die, opposite sidewalls of the second dielectric layer is within opposite sidewalls of the second die, and the first dielectric layer is physically connected to the second dielectric layer.